AsFigo - enabling opensource chip design and verification.

We opened our DVCon US ’26 Birds of a Feather session with the most electrifying—and anxious—question in the industry today: Is AI going to take your engineering job? To answer this, we turned to Clifford Cummings , world-renowned HDL Synthesis trainer, and Yatin Trivedi . Their consensus was a much-needed reality check: The tools are changing rapidly, but the need for fundamental engineering expertise is more critical than ever. The Trust Gap and the Junior Engineer Dilemma One of the biggest risks discussed in the panel is the assumption of correctness. AI tools can, and often do, get things "completely wrong." There is a growing concern that junior engineers, impressed by the speed of generative AI, often assume the output is correct and submit it without proper verification. This creates a dangerous Trust Gap . You cannot fix what you do not understand. Maintaining a strong foundational background in chip design is absolutely essential to identify, de...

This first installment of our DVCon US ’26 video series dives straight into a reality check that often gets lost in the hype of generative AI: The cost of a single "thought." In this segment, Srini (AsFigo) sits down with Asif ETV (HPCINFRA) to discuss why the transition to AI-native chip design isn't just a software challenge—it’s a massive infrastructure and economic hurdle. Watch the Full Segment :  In this 3-minute clip, watch Asif and Srini break down the economic reality of the modern AI-EDA stack and why optimizing for the right infrastructure is the only way to stay within budget while bringing AI into production. The Cost Explosion: Doing the Math on Hallucinations When we talk about "Agentic AI" in EDA, we imagine autonomous loops of design and verification. But as Asif ETV points out, the meter is always running, and it’s running faster than many teams realize. Sharing a startling metric from recent infrastructure experiments, the m...

While our previous posts focused on the strategic "Why," this post addresses the "How." Porting 50+ production-grade UVCs wasn't a matter of simple recompilation. It was an exercise in uncovering the delta between commercial simulator "permissiveness" and the strict reality of the SystemVerilog LRM and the Verilator execution model. Here are the some of the primary technical roadblocks we mapped and cleared.  You can learn lot more at our upcoming event on Thursda y, get your tickets today:  https://buytickets.at/asfigo/2091884   1. Strict LRM & Parsing Enforcement Commercial tools have historically been "lazy" with LRM enforcement. Verilator is not. Code that has run for years in proprietary silos often fails immediately here due to: SVA: Basic temporals do work, not complex ones. We have ported AHB, APB and AXI4-Lite SVA IPs to Verilator, so though this sounds very limiting, in reality, it is not that bad! Range Syntax: Not so...

UVM on Verilator Isn’t Impossible. It’s Just Hard. We Did It Anyway. The “standard” line in the industry: UVM and Verilator don’t mix. Enterprise-grade open-source verification is a fantasy. So we put that claim under load. ✔ 50+ production UVCs ported ✔ 35 + non-obvious failure modes uncovered ✔ Converted into UVMLint and SVALint rules ✔ AI guardrails to prevent regressions This post is the why and what; the how and numbers are for the room at Hacker Dojo.  This is production-grade code—the kind that tapes out chips—running on open-source infrastructure. The implication is bigger than a port: Reduced dependency on closed ecosystems. Negotiating leverage with EDA vendors. Strategic control over your verification stack. If you’re a semiconductor company exploring Verilator for serious IP, don’t start from scratch. Start from the team that already mapped the minefield. 📅 Join us at the Hacker Dojo Next Thursday, the AsFigo team...

In our previous post , we discussed the gap between AI "demos" and production-grade silicon. Today, we address the primary friction point preventing the industry from scaling AI-driven verification: The License Tax.  Registration:   https://forms.gle/WX6Hqwew2HfwDFmF8  The Math of Iteration "Agentic AI"—where autonomous loops generate, test, and fix RTL—relies on high-frequency iteration. For an AI agent to "learn" a fix or optimize a module, it may need to run hundreds or thousands of cycles through a verification engine. In a traditional environment, this is an economic impossibility. If every iterative trial pings a commercial tool seat—often costing upwards of $100,000 per license —the cost of the "agentic workforce" scales faster than its productivity. To make AI ROI viable, we must decouple the high-volume iterative cleaning from the high-cost final sign-off. The Production Milestone: Verilator + UVM is becoming a ...

The "AI in EDA" conversation is currently dominated by two extremes: the hype of autonomous agents and the reality of legacy verification constraints. While AI can generate code in seconds, the friction begins the moment that code hits a verification environment. Whether it’s the cost of commercial licenses or the risk of unvetted UVM sequences, the gap between a "cool demo" and a Production-Ready flow is wider than most realize. At DVCon 2026 , AsFigo is bridging that gap. We are hosting a Birds of a Feather (BoF) session to look at the full stack of Silicon-Ready AI . We’ve assembled a panel of industry veterans and disruptors to examine how we actually scale: The Workforce Shift: How global Centers of Excellence are integrating AI into existing UVM teams. The Agentic Loop: Startup founders on building autonomous verification cycles that actually close coverage. The Infrastructure: Solving the bottleneck of simulation licenses and specialized...

Remote link:  AsFigo UVM Verilator Bootcamp | Meeting-Join | Microsoft Teams For decades, the power of UVM (Universal Verification Methodology) has been locked behind the high-cost gates of commercial simulators. At AsFigo , we believe the future of silicon verification belongs to the community. We are breaking those gates down to empower a new generation of verification engineers. A Community Milestone The dream of open-source UVM is the result of a massive, multi-year industry effort. Foundations laid by the CHIPS Alliance, DARPA, Google, and Antmicro have reached a critical tipping point. This movement was fueled by the relentless technical contributions of pioneers such as Wilson Snyder, Geza Lore, Krzysztof Bieganski, et al. , whose work over the last several years made the "impossible" possible. The public breakthrough for UVM support in Verilator was announced in late 2023. On that very day, we at AsFigo successfully ported a complete APB UVC and...

The transition of SystemVerilog UVM environments to open-source simulators presents specific technical challenges. While Verilator 5.0+ has expanded support for various SystemVerilog constructs, the industry still lacks a documented and repeatable path for certain UVM-specific behaviors. In parallel, we aim to curate a public vault of UVM repositories that have been successfully ported to Verilator. AsFigo is initiating a collaborative effort to document these gaps, and we are looking for engineers, researchers, and students to contribute original UVM codebases to this effort.  Link to Google Form: Submit Your code base The Technical Focus This effort intentionally moves beyond minimal or illustrative examples. We are seeking unique, original UVM implementations that reflect realistic UVM environments and non-trivial SystemVerilog usage found in real-world verification flows. Infrastructure Components: Memo...

Linting SystemVerilog and UVM testbench code is crucial to maintain quality and compatibility. Many teams start by writing quick regex or string-search scripts to catch problematic patterns—like deprecated variables, disallowed constructs, or outdated API usage. While regex-based linting can be tempting due to its simplicity, it often leads to false failures and missed issues because SystemVerilog’s syntax and preprocessing are too complex for simple text matching. In this series, we will explore common linting scenarios, we introduced this in an earlier post here:   https://asfigo.blogspot.com/2025/02/linting-systemverilog-testbench-code.html  Below is the next one in this series with a concrete example - detecting deprecated UVM constructs like uvm_top , and demonstrate why a proper parser-based approach using tools like Google’s Verible is superior. A Quick, regex style lint example When maintaining UVM code for compatibility, one common check is to detect the use of u...

AsFigo invites you to our next technical session, focused on enabling semiconductor design teams to adopt open-source EDA tools—especially for testbench linting workflows. Remote-dial-in link:  UVMLint meetup - Cambridge, June 27 | Meeting-Join | Microsoft Teams 📍 Event: UVMLint & SVALint – Enablers to Move Your Chip Design Ahead 📅 Date: Friday, June 27, 2025 🕙 Time: 10:00 AM to 12:00 Noon (UK Time) 📌 Location: Wellington House, East Road, Cambridge, CB1 1BH, United Kingdom ☎ Phone: +44 1223 451000 🌐 Format: Hybrid (in-person & remote via Microsoft Teams) 💡 Cost: Free (registration required - https://forms.gle/upzLGyWJbRnbgRzU7 ) After a successful SVALint session in Reading, UK, we’re bringing this discussion to Cambridge—one of the UK’s most active semiconductor hubs. This event is geared toward engineers working in UVM based verification, formal verification, and testbench architecture using UVM and SVA. Ag...

SVALint Technical Meetup – Hybrid Event in Reading, UK AsFigo invites engineers and verification professionals to a focused technical meetup on SVALint —an open-source static verification abstraction linting framework. The event takes place on Sunday, 8 June 2025 , from 15:00 to 18:00 BST , hosted in a hybrid format (face-to-face and online). Register via:  https://forms.gle/qo8TBczXjNk62yAP6   Venue (In-Person) Meeting Room-5, First floor,  Novotel Reading Centre 25B Friar Street – RG1 1DP, Reading – United Kingdom T +44 (0) 1189 522 610 novotel.com/5432 Virtual Attendance Join via Microsoft Teams Why SVA Linting? SystemVerilog Assertions (SVA) play a critical role in ensuring correctness in complex verification environments. However, poorly structured assertions can hurt simulation performance, complicate debugging, or lead to ambiguous semantics. Linting SVAs helps catch such issues early—enforci...

Open Source Chip Design & Verification Event – Chennai 2025 Open Source Chip Design & Verification Event – Chennai 2025 The open-source hardware movement is shaping the future of semiconductor innovation, and you’re invited to be part of it! Join us at the Open Source Chip Design and Verification Event – Chennai 2025 , where experts in the field will share insights on open silicon, FPGA development, and SystemVerilog tooling. 📅 Date: April 5th, 2025 ⏰ Time: 3:00 PM – 5:00 PM 📍 Venue: Object Automation System Solutions Inc., Chennai Speakers Srinivasan Venkataramanan (AsFigo, UK)  – svck: A Lightweight and Extensible SystemVerilog Linter Kirupanithi RP (Object Automation) – Building Custom Chips with OpenPOWER Hemamalini Sundaram (VerifWorks) – UVMLint - case studies VP Sampath Ram (Bharath Semiconductor Society) – FPG...

Writing clean, maintainable, and consistent SystemVerilog testbench code is crucial for efficient verification. While functional correctness is the ultimate goal, enforcing coding styles helps improve readability, collaboration, and long-term maintainability. A well-structured codebase also reduces debugging time and ensures better reuse across projects. The Need for Linting and Style Enforcement Linting tools help enforce best practices by catching stylistic and structural violations early. Some fundamental style checks for SystemVerilog testbenches include: Encapsulation : Ensure proper use of class , local , protected , and virtual keywords to promote modularity. Line Length : Keep lines within a readable limit (e.g., 100 characters) to improve readability. Avoid Global Variables : Minimize or eliminate the use of global variables to prevent unintended side effects. Consistent Indentation and Naming : Follow a uniform inde...

The AsFigo Instance Extraction Utility ( $afPrHier ) is a Verilog Procedural Interface (VPI) app designed to automate the extraction of instance hierarchy data in Verilog simulations. It provides an efficient solution for analyzing and documenting the structural organization of Verilog designs, particularly in complex simulations. Purpose and Benefits Objective $afPrHier simplifies the process of collecting and documenting hierarchical relationships among modules and their instances in a Verilog simulation. It automates this task to reduce manual effort and potential errors. Features Automated Hierarchy Extraction: Gathers all module-instance relationships in a design and organizes them in a structured format. CSV-Based Reporting: Outputs hierarchy details in output_hier_info.csv with two essential columns: Module Name Instance Name ...

As open-source electronic design automation (EDA) tools continue to grow in popularity, events like WOSET (Workshop on Open-Source EDA Technology) have become essential for showcasing community-driven advancements. The 2024 edition of WOSET features an exciting lineup, including yoYoLint—a new open-source SystemVerilog RTL linter designed for Yosys. Built on AsFigo’s innovative "Build Your Own Linter" (BYOL) model, yoYoLint adds a much-needed layer of quality control to open-source HDL flows, addressing the often-overlooked process of HDL linting. Understanding the Role of HDL Linting in EDA Linting is a critical phase in hardware description language (HDL) design flows, helping enforce design rules, style guides, and best practices to ensure code quality. A robust HDL linter for SystemVerilog helps identify errors early, such as unused variables, unsupported constructs, potential race conditions, or missing sensitivity list items, enabling teams to produce clean, consist...

Waves2UVM is an app within the Go2UVM ecosystem that aids in the automatic generation of UVM testbenches from waveform data. This is especially valuable for engineers aiming to accelerate the design verification process of complex hardware systems. The tool works by translating waveform dumps (which capture signal behavior during simulations) into UVM verification components, thereby eliminating the manual coding typically required for testbench creation. The key advantage of Waves2UVM is its ability to work with formats like WaveDrom , offering a streamlined path from a structured, waveform data to a functional UVM testbench, which can be utilized within broader UVM verification flows. This improves productivity in hardware verification by reducing errors introduced during manual coding and speeding up the overall verification cycle. A recent customer usage of this handy technique deals with reproducing Formal Verification traces in simulation world. As Formal Verification tools such ...

OSDA is the premier European forum for open-source design automation. In 2024, this was co-hosted along with Design Automation & Test in Europe (DATE-24), the equivalent of USA's DAC.  Being held in the beautiful city of Valencia, Spain, AsFigo presented an insightful poster on "Adding Configurability to PySlint using TOML". This poster delved into the technical details and practical implications of integrating TOML (Tom's Obvious Minimal Language) into PySlint, a burgeoning SystemVerilog linter based on the open-source PySlang parser. The Need for Configurability in Linters Linting tools play a crucial role in maintaining code quality by enforcing coding standards and detecting potential issues early in the development process. SystemVerilog, a widely used language in ASIC and FPGA designs, often presents multiple ways to achieve the same functionality, making the role of linters even more ...

Opensource initiatives will do whole lot better with solid government support worldwide and with elections just around the corner, UK's industry is poised to make that push to the new government.  We joined the OpenUK " Open Manifesto " launch at King's College London on 3-Jul-2024. Led by  Amanda Brock , CEO at OpenUK this event boasted an impressive lineup of speakers and panel members and was well attended with diverse audience - from journalists to lawyers and of course many technical experts. Below is a quick reflection of what we found interesting and some pointers on our own work aligned in this direction. The illustrious speakers including Liz Rice, Amanda Brock, et. al., reflected on OpenUK's popular submarine model to quantify UK based opensource contributions and laid out a path for more tech experts to follow the model of building a "live CV on GitHub".  While the above is from 2023, the presenters did provide an update snapshot from 2024 hig...

 YAML, which stands for "YAML Ain't Markup Language," is a human-readable data serialization standard that is ideal for configuration files. We at AsFigo are helping customers adopt YAML for documenting VHDL (VHSIC Hardware Description Language) designs, especially at the interface level. One of the primary benefits of using YAML for VHDL designs is that it makes the information easier to parse and modify. This structured format allows for straightforward code generation and updates, significantly improving workflow efficiency. With YAML, you can create an organized, easy-to-read representation of VHDL entity interfaces, detailing ports, libraries, and other configurations. This structured approach not only aids developers in understanding and managing complex designs but also facilitates tool integration.   Below is a simple example YAML for a trivial up-down counter: Take a look at our opensource OSVVM Testbench generator project that utilizes this idea at: https://gith...

We at AsFigo AsFigo love Opensource. Off late we have been helping some European customers adopt modern verification techniques using VHDL. As a byproduct we have been building a Python based VHDL utility to generate a generic testbench based on OSVVM. While doing so, our team stumbled upon few subtle simulator issues, see: https://osvvm.org/forums/topic/sbrd-package-issue-with-modelsim-fpga-edition Hence, we wanted to try out NVC - a relatively new opensource VHDL compiler (https://www.nickg.me.uk/nvc/index.html). While there are pre-built binaries for several OS there, we couldn't locate one for WSL - Windows + WSL running Ubuntu. So, we decided to build it from source - isn't it the best thing about opensource - build missing pieces yourself?   So here is an Engineer's diary of how we got it up and running in less than 15 minutes! Fasten your seatbelt, off we go!  Follow the below steps: Grab the latest NVC tar ball from:  https://github.com/nickg/nvc/releases/ ....