Enhancing PySlint with TOML Configurability: Insights from OSDA 2024

OSDA is the premier European forum for open-source design automation. In 2024, this was co-hosted along with Design Automation & Test in Europe (DATE-24), the equivalent of USA's DAC. 


Being held in the beautiful city of Valencia, Spain, AsFigo presented an insightful poster on "Adding Configurability to PySlint using TOML".

This poster delved into the technical details and practical implications of integrating TOML (Tom's Obvious Minimal Language) into PySlint, a burgeoning SystemVerilog linter based on the open-source PySlang parser.

The Need for Configurability in Linters

Linting tools play a crucial role in maintaining code quality by enforcing coding standards and detecting potential issues early in the development process. SystemVerilog, a widely used language in ASIC and FPGA designs, often presents multiple ways to achieve the same functionality, making the role of linters even more significant. Customizability in these tools allows development teams to tailor linting rules to their specific coding styles and project requirements, enhancing both code consistency and functionality.

PySlint: Leveraging Open-Source for SystemVerilog Linting

PySlint is designed to leverage the capabilities of the open-source PySlang parser, providing a flexible and powerful linter for SystemVerilog. By allowing users to define custom linting rules via a Python API, PySlint facilitates a high degree of customization. However, as the tool gained traction, the need for an intuitive and structured configuration method became apparent.




Integrating TOML for Enhanced Configurability

TOML, known for its simplicity and readability, emerged as an ideal choice for configuring PySlint. The integration of TOML into PySlint enables users to easily define and manage linting rules and settings in a straightforward, human-readable format. This approach not only simplifies the configuration process but also enhances the overall usability of PySlint.


The poster presented at OSDA 2024 outlined the following key points:

  • Configurability Features: Detailed how TOML can be used to enable/disable various linting rules and configurations, making it easier for users to adapt PySlint to their specific needs.
  • Implementation Details: Discussed the technical aspects of integrating TOML with PySlint, including challenges faced and solutions implemented.
  • User Case Studies: Highlighted early use cases from industry projects such as the tinyODIN spiking neural network processor and OpenTitan IPs. These case studies demonstrated the practical benefits of TOML-based configurations in real-world scenarios, showcasing improvements in code consistency and reduced risk of functional errors and race conditions.

Conclusion and Future Prospects

The addition of TOML configurability to PySlint marks a significant step forward in the tool's development, making it more accessible and useful for a broader range of users. AsFigo's presentation at OSDA 2024 not only underscored the importance of customizable linting tools but also set the stage for further innovations in open-source design automation.

For more technical details and to explore PySlint, you can visit the PySlint GitHub repository and the OSDA official website.






Comments

  1. pgOctober 7, 2026 at 5:16 AM

    The article provides a useful look at how configurability can improve a SystemVerilog linting tool, particularly through the integration of TOML into PySlint. The discussion of custom linting rules is important because different ASIC and FPGA development teams may follow different coding standards, making configurable analysis valuable for maintaining consistency while detecting potential issues early.

    The explanation of PySlint's use of the open-source PySlang parser also shows how Python can be used to build specialized development tools. For readers who want to strengthen their Python programming foundation before working with tools such as parsers, APIs, and configurable automation utilities, a Python Online Course can provide a useful starting point.

    ReplyDelete
  2. pgOctober 7, 2026 at 5:16 AM

    The move from Python API-based configuration toward a structured TOML configuration approach is particularly interesting because it can make customization easier to manage as a project grows. Learning through a Python Online Training program can also help developers build the programming skills needed to work with configuration-driven tools and automation workflows.

    ReplyDelete

Post a Comment

Popular posts from this blog

Cracking the UVM-Verilator Code: 50+ IPs, AI Guardrails, and the Open-Source North Star

UVM on Verilator Isn’t Impossible. It’s Just Hard. We Did It Anyway. The “standard” line in the industry: UVM and Verilator don’t mix. Enterprise-grade open-source verification is a fantasy. So we put that claim under load. ✔ 50+ production UVCs ported ✔ 35 + non-obvious failure modes uncovered ✔ Converted into UVMLint and SVALint rules ✔ AI guardrails to prevent regressions This post is the why and what; the how and numbers are for the room at Hacker Dojo.  This is production-grade code—the kind that tapes out chips—running on open-source infrastructure. The implication is bigger than a port: Reduced dependency on closed ecosystems. Negotiating leverage with EDA vendors. Strategic control over your verification stack. If you’re a semiconductor company exploring Verilator for serious IP, don’t start from scratch. Start from the team that already mapped the minefield. 📅 Join us at the Hacker Dojo Next Thursday, the AsFigo team...
Read more

Open-Source Chip Design & Verification Bootcamp — Programme & Speakers

Bengaluru | Monday, 31 August 2026 | 1:00–5:30 PM IST  | 8:30–13:00 BST (UK) | 9:30 AM–14:00 PM CEST (Central Europe) REGISTER NOW - https://tinyurl.com/asfigoblr26    Remote dial-in link:  AsFigo: Open-Source Chip Design & Verification Bootcamp | Meeting-Join | Microsoft Teams Following our earlier announcement, the programme and speakers for the AsFigo Open-Source Chip Design & Verification Bootcamp are now taking shape. For background and the story behind this event, see our earlier post . Event Details AsFigo invites working professionals, researchers, students and semiconductor enthusiasts to participate in this interactive technical meetup focused on open-source chip design and verification. Date: Monday, 31 August 2026 Time: 1:00–5:30 PM IST | 8:30 AM –13:00 PM BST (UK) | 9:30 AM–14:00 PM CEST (Central Europe) Format: Hybrid Host: AsFigo In-person: BHIVE Premium Bellandur Campus, Ratan Tata Conf room | Ground Floor; ...
Read more

Call for Collaboration: Seeking Public UVM Environments for Verilator 5.0+ Porting

The transition of SystemVerilog UVM environments to open-source simulators presents specific technical challenges. While Verilator 5.0+ has expanded support for various SystemVerilog constructs, the industry still lacks a documented and repeatable path for certain UVM-specific behaviors. In parallel, we aim to curate a public vault of UVM repositories that have been successfully ported to Verilator. AsFigo is initiating a collaborative effort to document these gaps, and we are looking for engineers, researchers, and students to contribute original UVM codebases to this effort.  Link to Google Form: Submit Your code base The Technical Focus This effort intentionally moves beyond minimal or illustrative examples. We are seeking unique, original UVM implementations that reflect realistic UVM environments and non-trivial SystemVerilog usage found in real-world verification flows. Infrastructure Components: Memo...
Read more