Building a Functional Coverage Model for VHDL Design Using BenchBot and OSVVM
In VHDL-based digital design, ensuring that every key aspect of your design is tested comprehensively is critical. Functional coverage plays a pivotal role in this process by quantifying how thoroughly the testbench exercises the design's functionality. In this article, we will demonstrate how to create a functional coverage model for a simple up/down counter ( af_up_dn_counter ) using BenchBot, a Python tool for generating templated testbenches, in conjunction with OSVVM (Open Source VHDL Verification Methodology), which provides a robust functional coverage package. Setting Up the Testbench with BenchBot BenchBot, a Python app simplifies the creation of VHDL testbenches by generating template files. It serves as a starting point rather than a fully functional testbench with all tests. However, it goes way beyond basic testbench by creating functional coverage model for all relevant DUT ports. We will show an example of this below. Overview of the Design The design ...