AsFigo - enabling opensource chip design and verification.

AsFigo invites you to our next technical session, focused on enabling semiconductor design teams to adopt open-source EDA tools—especially for testbench linting workflows. Remote-dial-in link:  UVMLint meetup - Cambridge, June 27 | Meeting-Join | Microsoft Teams 📍 Event: UVMLint & SVALint – Enablers to Move Your Chip Design Ahead 📅 Date: Friday, June 27, 2025 🕙 Time: 10:00 AM to 12:00 Noon (UK Time) 📌 Location: Wellington House, East Road, Cambridge, CB1 1BH, United Kingdom ☎ Phone: +44 1223 451000 🌐 Format: Hybrid (in-person & remote via Microsoft Teams) 💡 Cost: Free (registration required - https://forms.gle/upzLGyWJbRnbgRzU7 ) After a successful SVALint session in Reading, UK, we’re bringing this discussion to Cambridge—one of the UK’s most active semiconductor hubs. This event is geared toward engineers working in UVM based verification, formal verification, and testbench architecture using UVM and SVA. Ag...

In the intricate world of semiconductor design verification, the interplay between formal verification and simulation-based approaches continues to evolve. A recent case study highlights the complementary nature of these methodologies and underscores the importance of a comprehensive verification strategy. The Scenario During a routine IP verification using formal tools and SystemVerilog Assertions (SVA), a bug was uncovered that had previously eluded detection in subsystem-level simulation. This discovery prompted a deeper investigation into the verification process and the tools employed. Formal Verification's Unique Strength Formal verification's ability to exhaustively explore state spaces within specified bounds allowed it to uncover a corner case that simulation had missed. This strength stems from formal tools' capacity to: Examine all possible states and input combinations Operate without the need for specific test vectors Explore deep states that might be...

Waves2UVM is an app within the Go2UVM ecosystem that aids in the automatic generation of UVM testbenches from waveform data. This is especially valuable for engineers aiming to accelerate the design verification process of complex hardware systems. The tool works by translating waveform dumps (which capture signal behavior during simulations) into UVM verification components, thereby eliminating the manual coding typically required for testbench creation. The key advantage of Waves2UVM is its ability to work with formats like WaveDrom , offering a streamlined path from a structured, waveform data to a functional UVM testbench, which can be utilized within broader UVM verification flows. This improves productivity in hardware verification by reducing errors introduced during manual coding and speeding up the overall verification cycle. A recent customer usage of this handy technique deals with reproducing Formal Verification traces in simulation world. As Formal Verification tools such ...