MathLib - computing modulo on real numbers in SystemVerilog
Think of noise filtering algorithms, floating point computations etc. - a handy operator in such circumstances is modulo - loosely defined as a function that returns remainder after division (however, there is a close cousin rem - for later discussion). System designers often use mod function to perform certain periodic functions, DSP algorithms etc. When such systems are implemented in hardware, designers often use Verilog to capture the same intent. Verilog (or SystemVerilog) has % operator in-built to provide basic support for modulo computation - it works just fine for unsigned integers. However, in behavioral models, testbenches and AMS models, often real numbers get involved and suddenly you get an error from your favorite HDL simulator as below (Verilator as example): %Error: t.sv:7:32: Expected integral (non-real) input to MODDIV : ... In instance m 7 | $display ("3.2 MOD 1: %f", 3.2%1...