AsFigo - enabling opensource chip design and verification.

We opened our DVCon US ’26 Birds of a Feather session with the most electrifying—and anxious—question in the industry today: Is AI going to take your engineering job? To answer this, we turned to Clifford Cummings , world-renowned HDL Synthesis trainer, and Yatin Trivedi . Their consensus was a much-needed reality check: The tools are changing rapidly, but the need for fundamental engineering expertise is more critical than ever. The Trust Gap and the Junior Engineer Dilemma One of the biggest risks discussed in the panel is the assumption of correctness. AI tools can, and often do, get things "completely wrong." There is a growing concern that junior engineers, impressed by the speed of generative AI, often assume the output is correct and submit it without proper verification. This creates a dangerous Trust Gap . You cannot fix what you do not understand. Maintaining a strong foundational background in chip design is absolutely essential to identify, de...

In our previous installment, we looked at the brutal $10-per-query economics of AI-EDA. But even if the cost of inference drops to near zero, a deeper technical question remains: Can you actually trust the answer? Continuing our series from the DVCon US ’26 Birds of a Feather session, Yatin Trivedi , Head, Semiconductor Center of Excellence (CoE) at Capgemini Engineering, shared the results of a high-stakes experiment that serves as a reality check for the industry’s "AI-everything" race. It highlights a massive maturity gap that every verification lead needs to understand before they integrate LLMs into their sign-off flow. The Experiment: Grading the Plan Yatin’s team conducted a controlled trial: they took a final design specification and a manually crafted, human-verified verification plan. They then asked four leading AI platforms to "grade" that plan for completeness. Could the AI identify gaps in the testing strategy before tape-out? I...

This first installment of our DVCon US ’26 video series dives straight into a reality check that often gets lost in the hype of generative AI: The cost of a single "thought." In this segment, Srini (AsFigo) sits down with Asif ETV (HPCINFRA) to discuss why the transition to AI-native chip design isn't just a software challenge—it’s a massive infrastructure and economic hurdle. Watch the Full Segment :  In this 3-minute clip, watch Asif and Srini break down the economic reality of the modern AI-EDA stack and why optimizing for the right infrastructure is the only way to stay within budget while bringing AI into production. The Cost Explosion: Doing the Math on Hallucinations When we talk about "Agentic AI" in EDA, we imagine autonomous loops of design and verification. But as Asif ETV points out, the meter is always running, and it’s running faster than many teams realize. Sharing a startling metric from recent infrastructure experiments, the m...

In our previous post , we discussed the gap between AI "demos" and production-grade silicon. Today, we address the primary friction point preventing the industry from scaling AI-driven verification: The License Tax.  Registration:   https://forms.gle/WX6Hqwew2HfwDFmF8  The Math of Iteration "Agentic AI"—where autonomous loops generate, test, and fix RTL—relies on high-frequency iteration. For an AI agent to "learn" a fix or optimize a module, it may need to run hundreds or thousands of cycles through a verification engine. In a traditional environment, this is an economic impossibility. If every iterative trial pings a commercial tool seat—often costing upwards of $100,000 per license —the cost of the "agentic workforce" scales faster than its productivity. To make AI ROI viable, we must decouple the high-volume iterative cleaning from the high-cost final sign-off. The Production Milestone: Verilator + UVM is becoming a ...

The "AI in EDA" conversation is currently dominated by two extremes: the hype of autonomous agents and the reality of legacy verification constraints. While AI can generate code in seconds, the friction begins the moment that code hits a verification environment. Whether it’s the cost of commercial licenses or the risk of unvetted UVM sequences, the gap between a "cool demo" and a Production-Ready flow is wider than most realize. At DVCon 2026 , AsFigo is bridging that gap. We are hosting a Birds of a Feather (BoF) session to look at the full stack of Silicon-Ready AI . We’ve assembled a panel of industry veterans and disruptors to examine how we actually scale: The Workforce Shift: How global Centers of Excellence are integrating AI into existing UVM teams. The Agentic Loop: Startup founders on building autonomous verification cycles that actually close coverage. The Infrastructure: Solving the bottleneck of simulation licenses and specialized...