AsFigo - enabling opensource chip design and verification.

Ensuring Correctness and Observability in SPI Signal Assertions In SPI verification, a fundamental requirement is that all active signals— SCLK , MOSI , and MISO —must be fully defined whenever chip-select is asserted . Any unknown or high-impedance state ( X or Z ) can compromise data integrity and lead to subtle bugs. SystemVerilog Assertions (SVA) offer a natural mechanism to codify this requirement. When applied thoughtfully, they enforce correctness and enhance diagnostic clarity. Clear, modular assertions make failures immediately understandable, particularly in larger testbenches, which aligns well with style-aware analysis tools. Issue 1: Functional Correctness A common misstep is to combine multiple signals in a single $isunknown call with a logical AND: // INCORRECT $isunknown(spiclk && mosi && miso) The problem: logical AND short-circuits evaluation, potentially masking unknown states. Example: spiclk = X, mosi = 0, miso = 1 spiclk ...

AsFigo invites you to our next technical session, focused on enabling semiconductor design teams to adopt open-source EDA tools—especially for testbench linting workflows. Remote-dial-in link:  UVMLint meetup - Cambridge, June 27 | Meeting-Join | Microsoft Teams 📍 Event: UVMLint & SVALint – Enablers to Move Your Chip Design Ahead 📅 Date: Friday, June 27, 2025 🕙 Time: 10:00 AM to 12:00 Noon (UK Time) 📌 Location: Wellington House, East Road, Cambridge, CB1 1BH, United Kingdom ☎ Phone: +44 1223 451000 🌐 Format: Hybrid (in-person & remote via Microsoft Teams) 💡 Cost: Free (registration required - https://forms.gle/upzLGyWJbRnbgRzU7 ) After a successful SVALint session in Reading, UK, we’re bringing this discussion to Cambridge—one of the UK’s most active semiconductor hubs. This event is geared toward engineers working in UVM based verification, formal verification, and testbench architecture using UVM and SVA. Ag...

In the intricate world of semiconductor design verification, the interplay between formal verification and simulation-based approaches continues to evolve. A recent case study highlights the complementary nature of these methodologies and underscores the importance of a comprehensive verification strategy. The Scenario During a routine IP verification using formal tools and SystemVerilog Assertions (SVA), a bug was uncovered that had previously eluded detection in subsystem-level simulation. This discovery prompted a deeper investigation into the verification process and the tools employed. Formal Verification's Unique Strength Formal verification's ability to exhaustively explore state spaces within specified bounds allowed it to uncover a corner case that simulation had missed. This strength stems from formal tools' capacity to: Examine all possible states and input combinations Operate without the need for specific test vectors Explore deep states that might be...

The SystemVerilog Assertions Handbook The SystemVerilog Assertions Handbook is a popular publication in the field of hardware design and verification. Authored by Ben Cohen, Ajeetha Kumari, Srinivasan Venkataramanan, and Lisa Piper, it became the world’s first book solely dedicated to SystemVerilog Assertions (SVA) when it was first published in 2005. At a time when SystemVerilog was gaining widespread acceptance, the authors recognized the need for a focused resource that could demystify assertions and provide engineers with practical insights into their use in modern verification flows. Now in its fourth edition, the handbook has evolved in tandem with advancements in the SVA standard, making it an indispensable reference for both beginners and experienced verification engineers. What sets this book apart is its combination of theory and practical examples, offering real-world insights into the effective use of SVA for improving design verification quality....

During a recent conversation with a PhD student in the USA, our team highlighted some of our team's recent work in promoting opensource EDA tools for SystemVerilog Assertions (SVA). Below is an excerpt from that conversation for wider audience. For opensource SVA tools, Verilator does have some support. We have released  SVA for APB - running in Verilator:  https://github.com/AsFigo/af_ sva_apb We presented this work at LatchUp 2023 event at Santa Barbara:  https://www.youtube. com/watch?v=vMscbHq1vd8   We also have developed an opensource linter for SV, SVA, DPI etc. see:  https://github.com/ AsFigo/pyslint