AsFigo - enabling opensource chip design and verification.

We opened our DVCon US ’26 Birds of a Feather session with the most electrifying—and anxious—question in the industry today: Is AI going to take your engineering job? To answer this, we turned to Clifford Cummings , world-renowned HDL Synthesis trainer, and Yatin Trivedi . Their consensus was a much-needed reality check: The tools are changing rapidly, but the need for fundamental engineering expertise is more critical than ever. The Trust Gap and the Junior Engineer Dilemma One of the biggest risks discussed in the panel is the assumption of correctness. AI tools can, and often do, get things "completely wrong." There is a growing concern that junior engineers, impressed by the speed of generative AI, often assume the output is correct and submit it without proper verification. This creates a dangerous Trust Gap . You cannot fix what you do not understand. Maintaining a strong foundational background in chip design is absolutely essential to identify, de...

The "AI in EDA" conversation is currently dominated by two extremes: the hype of autonomous agents and the reality of legacy verification constraints. While AI can generate code in seconds, the friction begins the moment that code hits a verification environment. Whether it’s the cost of commercial licenses or the risk of unvetted UVM sequences, the gap between a "cool demo" and a Production-Ready flow is wider than most realize. At DVCon 2026 , AsFigo is bridging that gap. We are hosting a Birds of a Feather (BoF) session to look at the full stack of Silicon-Ready AI . We’ve assembled a panel of industry veterans and disruptors to examine how we actually scale: The Workforce Shift: How global Centers of Excellence are integrating AI into existing UVM teams. The Agentic Loop: Startup founders on building autonomous verification cycles that actually close coverage. The Infrastructure: Solving the bottleneck of simulation licenses and specialized...