Posts

Reviving OVL for the AI era, via opensource

RTL is getting cheaper to produce. Whether it comes from a teammate, a script or an AI assistant, someone still has to decide if it's correct, and that check shouldn't depend on a license seat. Our bet is that simple, always-on assertions are a good answer. Accellera's Open Verification Library (OVL) is 55 ready-made checkers written as plain HDL modules. You instantiate one next to the logic it watches, and it tells you when a rule is broken. They're vendor-neutral and tool-agnostic. That is the shape of guardrail a CI job running an open-source simulator can use on every commit. OVL's last release was in 2014, and its working group is listed as inactive. The simulators have moved on, and the library hasn't. So we're doing something about it. af_ovl: OVL 2.8.1, revamped for open-source simulators The first target is Icarus Verilog. Here's what you get today: Silent checkers now speak up. Four checkers ( ovl_bits , ovl_mutex , ovl_code_distan...
Post a Comment
Read more

Key 7 Takeaways from Satish Sridharan's Open-Source Chip Design Keynote

  From "Nobody Got Fired for Using Mainstream Tools" to AI-Native Chip Design: Key Takeaways from Satish Sridharan's Keynote Keynote at the AsFigo Open-Source Chip Design & Verification Bootcamp, 31 August 2026, Bengaluru Satish Sridharan, Senior Director of Digital (Timing Business Unit) at Aura Semiconductor, opened the AsFigo bootcamp with a keynote tracing the arc of open source in chip design — from a cost play to a genuine engine of innovation, now accelerating further under AI. With over 30 years in the industry (Aura Semiconductor, prior stints at Infinera and Vitesse Semiconductors), and hands-on experience with mixed-signal verification challenges, he brought a design-side veteran's perspective to a room mostly focused on verification. Here are the key takeaways. 1. The EDA industry's own history explains why open source was ever in doubt Satish set the stage with a quick tour of how far EDA tooling has come — from manually placed schematic-capture d...
Post a Comment
Read more

Opensource Bootcamp Update: OSVVM Joins the Lineup, Keynote Confirmed, Agenda Extended

A few updates since our first announcement for the Open-Source Chip Design & Verification Bootcamp (31 Aug 2026, BHIVE Bellandur, Bengaluru + Hybrid): REGISTER NOW - https://tinyurl.com/asfigoblr26    Remote dial-in link: AsFigo: Open-Source Chip Design & Verification Bootcamp | Meeting-Join | Microsoft Teams Keynote confirmed: Satish Sridharan, Sr. Director Digital, Aura Semiconductor New speaker added: Jim Lewis, chief architect of OSVVM, presenting "OSVVM: A Better Way to Verify Your VHDL Designs" New talk added: CNSTLint (constraint linting) by Nambi JU Agenda extended to 5:30 PM for more depth and Q&A across sessions Full lineup: Updated Agenda — Monday, 31 August 2026 | 1:00 PM – 5:30 PM IST BHIVE Premium Bellandur Campus, Bengaluru (Hybrid) Time (IST) Session Speaker Mode 1:00 – 1:10 PM Welcome & Intro Srinivasan Venkataramanan, AsFigo In-person ...
Post a Comment
Read more

Beyond RTL Lint: 90+ Rules for SystemVerilog Assertions, Constraints, and Coverage

Back in 2023, we started building open-source lint tools for the parts of SystemVerilog that commercial linters tend to treat as an afterthought — assertions, constraint blocks, and functional coverage. What began as a handful of rules has grown into a substantial rule set: SVALint , CNSTLint , and FCOVLint now collectively cover over 90 lint rules, all built on the Verible parser and the BYOL (Build Your Own Linter) framework. This post highlights the rules that catch real bugs, silent misbehaviour, and tool-specific pitfalls — not naming conventions. Full rationale, violation examples, and correct usage are in the linked docs. SVALint — Assertion Linting (52 rules) Repo: github.com/AsFigo/svalint  |  Docs: asfigo.github.io/svalint/ SVA is deceptively easy to write incorrectly. These rules catch issues that compile cleanly, pass elaboration, and then silently misbehave in simulation or formal verification. Rule ID Bug it catches DELAY_BEFORE_ROSE D...
Post a Comment
Read more

Hello World - Verilator + UVM example - Quickstart

Running UVM on Verilator: Introducing af_vlt_uvm Over the past year, AsFigo has been contacted by verification engineers across the globe — 30-year veterans, interns, junior engineers - from the US and UK, the EU, and junior engineers in India — all asking the same questions:  How do I get UVM running on Verilator?  Is there a working Makefile?  A quick example I can try?  The pattern is clear: Verilator is well known and widely used, UVM is the industry standard, but getting the two to work together is still a stumbling block for most engineers. We built af_vlt_uvm to fix that — a quickstart that gets you from git clone to a running UVM simulation on Verilator in minutes. Why Verilator + UVM? The EDA community has shown strong interest in running UVM testbenches on Verilator. The appeal is obvious: Verilator is free, extremely fast, and widely available on CI/CD infrastructure. The challenge is equally obvious: UVM was written for commercial simulators an...
Post a Comment
Read more

Open-Source Chip Design & Verification Bootcamp — Programme & Speakers

Bengaluru | Monday, 31 August 2026 | 1:00–5:30 PM IST  | 8:30–13:00 BST (UK) | 9:30 AM–14:00 PM CEST (Central Europe) REGISTER NOW - https://tinyurl.com/asfigoblr26    Remote dial-in link:  AsFigo: Open-Source Chip Design & Verification Bootcamp | Meeting-Join | Microsoft Teams Following our earlier announcement, the programme and speakers for the AsFigo Open-Source Chip Design & Verification Bootcamp are now taking shape. For background and the story behind this event, see our earlier post . Event Details AsFigo invites working professionals, researchers, students and semiconductor enthusiasts to participate in this interactive technical meetup focused on open-source chip design and verification. Date: Monday, 31 August 2026 Time: 1:00–5:30 PM IST | 8:30 AM –13:00 PM BST (UK) | 9:30 AM–14:00 PM CEST (Central Europe) Format: Hybrid Host: AsFigo In-person: BHIVE Premium Bellandur Campus, Ratan Tata Conf room | Ground Floor; ...
Post a Comment
Read more

Open-Source Chip Design & Verification bootcamp: Bengaluru, 31 August 2026

AsFigo is organising a 3-hour hybrid bootcamp on open-source chip design and verification in Bengaluru on Monday, 31 August 2026, immediately ahead of DVCon India 2026. Date: Monday, 31 August 2026 Time: 1:00–4:00 PM IST Location: Bengaluru, ORR / Bellandur area — venue to be confirmed Format: Hybrid Cost: Free to attend Registration: Required The event brings together a deliberately diverse set of open-source verification projects and approaches — from UVM and Verilator to Rust-based verification, formal, functional-coverage linting, OSVVM and SystemVerilog Assertions. The aim is not to promote one particular tool or methodology. It is to bring together people working on different parts of the ecosystem and explore what is becoming possible with open-source verification. A journey that started well before this event AsFigo's work in open-source verification builds on a much longer history in design verification. Our founders, Ajeetha Kumari and Srinivasan Venkataramanan, ha...
1 comment
Read more