AsFigo - enabling opensource chip design and verification.

A few updates since our first announcement for the Open-Source Chip Design & Verification Bootcamp (31 Aug 2026, BHIVE Bellandur, Bengaluru + Hybrid): REGISTER NOW - https://tinyurl.com/asfigoblr26    Remote dial-in link: AsFigo: Open-Source Chip Design & Verification Bootcamp | Meeting-Join | Microsoft Teams Keynote confirmed: Satish Sridharan, Sr. Director Digital, Aura Semiconductor New speaker added: Jim Lewis, chief architect of OSVVM, presenting "OSVVM: A Better Way to Verify Your VHDL Designs" New talk added: CNSTLint (constraint linting) by Nambi JU Agenda extended to 5:30 PM for more depth and Q&A across sessions Full lineup: Updated Agenda — Monday, 31 August 2026 | 1:00 PM – 5:30 PM IST BHIVE Premium Bellandur Campus, Bengaluru (Hybrid) Time (IST) Session Speaker Mode 1:00 – 1:10 PM Welcome & Intro Srinivasan Venkataramanan, AsFigo In-person ...

Back in 2023, we started building open-source lint tools for the parts of SystemVerilog that commercial linters tend to treat as an afterthought — assertions, constraint blocks, and functional coverage. What began as a handful of rules has grown into a substantial rule set: SVALint , CNSTLint , and FCOVLint now collectively cover over 90 lint rules, all built on the Verible parser and the BYOL (Build Your Own Linter) framework. This post highlights the rules that catch real bugs, silent misbehaviour, and tool-specific pitfalls — not naming conventions. Full rationale, violation examples, and correct usage are in the linked docs. SVALint — Assertion Linting (52 rules) Repo: github.com/AsFigo/svalint  |  Docs: asfigo.github.io/svalint/ SVA is deceptively easy to write incorrectly. These rules catch issues that compile cleanly, pass elaboration, and then silently misbehave in simulation or formal verification. Rule ID Bug it catches DELAY_BEFORE_ROSE D...

Running UVM on Verilator: Introducing af_vlt_uvm Over the past year, AsFigo has been contacted by verification engineers across the globe — 30-year veterans, interns, junior engineers - from the US and UK, the EU, and junior engineers in India — all asking the same questions:  How do I get UVM running on Verilator?  Is there a working Makefile?  A quick example I can try?  The pattern is clear: Verilator is well known and widely used, UVM is the industry standard, but getting the two to work together is still a stumbling block for most engineers. We built af_vlt_uvm to fix that — a quickstart that gets you from git clone to a running UVM simulation on Verilator in minutes. Why Verilator + UVM? The EDA community has shown strong interest in running UVM testbenches on Verilator. The appeal is obvious: Verilator is free, extremely fast, and widely available on CI/CD infrastructure. The challenge is equally obvious: UVM was written for commercial simulators an...

Bengaluru | Monday, 31 August 2026 | 1:00–5:30 PM IST  | 8:30–13:00 BST (UK) | 9:30 AM–14:00 PM CEST (Central Europe) REGISTER NOW - https://tinyurl.com/asfigoblr26    Remote dial-in link:  AsFigo: Open-Source Chip Design & Verification Bootcamp | Meeting-Join | Microsoft Teams Following our earlier announcement, the programme and speakers for the AsFigo Open-Source Chip Design & Verification Bootcamp are now taking shape. For background and the story behind this event, see our earlier post . Event Details AsFigo invites working professionals, researchers, students and semiconductor enthusiasts to participate in this interactive technical meetup focused on open-source chip design and verification. Date: Monday, 31 August 2026 Time: 1:00–5:30 PM IST | 8:30 AM –13:00 PM BST (UK) | 9:30 AM–14:00 PM CEST (Central Europe) Format: Hybrid Host: AsFigo In-person: BHIVE Premium Bellandur Campus, Ratan Tata Conf room | Ground Floor; ...

AsFigo is organising a 3-hour hybrid bootcamp on open-source chip design and verification in Bengaluru on Monday, 31 August 2026, immediately ahead of DVCon India 2026. Date: Monday, 31 August 2026 Time: 1:00–4:00 PM IST Location: Bengaluru, ORR / Bellandur area — venue to be confirmed Format: Hybrid Cost: Free to attend Registration: Required The event brings together a deliberately diverse set of open-source verification projects and approaches — from UVM and Verilator to Rust-based verification, formal, functional-coverage linting, OSVVM and SystemVerilog Assertions. The aim is not to promote one particular tool or methodology. It is to bring together people working on different parts of the ecosystem and explore what is becoming possible with open-source verification. A journey that started well before this event AsFigo's work in open-source verification builds on a much longer history in design verification. Our founders, Ajeetha Kumari and Srinivasan Venkataramanan, ha...

Why Regex Is the Wrong Abstraction for SystemVerilog Coverage Linting When building a lint rule for SystemVerilog functional coverage, it is tempting to start with a regular expression. The problem can initially appear simple: find array-based coverpoint bins, calculate how many bins they expand into, and report a violation if the count exceeds the supported limit. A first implementation might read the source file, remove comments, and search for patterns such as bins foo[] = {[0:2048]}; . As a first-cut implementation, this is perfectly reasonable. It is small, easy to prototype, and useful for validating the basic rule logic. The problem is that regular expressions operate on source text , while a lint rule needs to reason about language structure . Consider: bins values[] = { [0:2048], [3000:4000] }; The rule now needs to understand that this is one array-bin declaration containing multiple ranges, and calculate the expansion represented by those ranges. A re...