AsFigo - enabling opensource chip design and verification.

The "AI in EDA" conversation is currently dominated by two extremes: the hype of autonomous agents and the reality of legacy verification constraints. While AI can generate code in seconds, the friction begins the moment that code hits a verification environment. Whether it’s the cost of commercial licenses or the risk of unvetted UVM sequences, the gap between a "cool demo" and a Production-Ready flow is wider than most realize. At DVCon 2026 , AsFigo is bridging that gap. We are hosting a Birds of a Feather (BoF) session to look at the full stack of Silicon-Ready AI . We’ve assembled a panel of industry veterans and disruptors to examine how we actually scale: The Workforce Shift: How global Centers of Excellence are integrating AI into existing UVM teams. The Agentic Loop: Startup founders on building autonomous verification cycles that actually close coverage. The Infrastructure: Solving the bottleneck of simulation licenses and specialized...

For decades, the power of UVM (Universal Verification Methodology) has been locked behind the high-cost gates of commercial simulators. At AsFigo , we believe the future of silicon verification belongs to the community. We are breaking those gates down to empower a new generation of verification engineers. A Community Milestone The dream of open-source UVM is the result of a massive, multi-year industry effort. Foundations laid by the CHIPS Alliance, DARPA, Google, and Antmicro have reached a critical tipping point. This movement was fueled by the relentless technical contributions of pioneers such as Wilson Snyder, Geza Lore, Krzysztof Bieganski, et al. , whose work over the last several years made the "impossible" possible. The public breakthrough for UVM support in Verilator was announced in late 2023. On that very day, we at AsFigo successfully ported a complete APB UVC and published our journey here . AsFigo’s Commitment to the Core We d...

The transition of SystemVerilog UVM environments to open-source simulators presents specific technical challenges. While Verilator 5.0+ has expanded support for various SystemVerilog constructs, the industry still lacks a documented and repeatable path for certain UVM-specific behaviors. In parallel, we aim to curate a public vault of UVM repositories that have been successfully ported to Verilator. AsFigo is initiating a collaborative effort to document these gaps, and we are looking for engineers, researchers, and students to contribute original UVM codebases to this effort.  Link to Google Form: Submit Your code base The Technical Focus This effort intentionally moves beyond minimal or illustrative examples. We are seeking unique, original UVM implementations that reflect realistic UVM environments and non-trivial SystemVerilog usage found in real-world verification flows. Infrastructure Components: Memo...

Technical Meetup: Open Source Chip Design and Verification AsFigo is hosting a technical session dedicated to the advancements in open-source hardware design and verification.  Register for the Event   Please use the following MS Teams link to join the event on January 9th at 2 PM: https://teams.live.com/meet/9333303774354?p=bVhyGy7i3BGuUuiqpX This session is designed for engineers and practitioners looking to integrate modern automation and open-source methodologies into their silicon workflows. The discussion will center on the practical application of GenAI in hardware development, alongside a deep dive into specialized linting tools including SVALint, FPGALint, and UVMLint. Event Details Date: Friday, January 9th, 2026 Time:  2:00 PM – 5:00 PM IST Format: Hybrid (In-person and Remote) Venue:    Seminar Hall/Room No. EL-106, Centre for Advanced Studies in Electroni...

Is your DPI-enabled SystemVerilog simulation running slow? Are you looking for ways to improve performance? Sometimes, a small remodelling of your DPI functions and using pure functions can help significantly. The Direct Programming Interface (DPI) allows SystemVerilog to interact with C code. Among the DPI constructs, pure functions are special because they are side-effect free and predictable. Using them correctly can improve simulation speed and reliability. However, SystemVerilog LRM imposes several subtle restrictions on imported pure  functions. Let's delve into one such nuance today a bit deeper! Referential Transparency Referential transparency is a concept from programming. An expression is referentially transparent if it can always be replaced by its value without changing the behaviour of the program. For example: The expression 2 + 3 can always be replaced with 5 . The expression rand() cannot, since each call may give a different result. In SystemVer...

Ensuring Correctness and Observability in SPI Signal Assertions In SPI verification, a fundamental requirement is that all active signals— SCLK , MOSI , and MISO —must be fully defined whenever chip-select is asserted . Any unknown or high-impedance state ( X or Z ) can compromise data integrity and lead to subtle bugs. SystemVerilog Assertions (SVA) offer a natural mechanism to codify this requirement. When applied thoughtfully, they enforce correctness and enhance diagnostic clarity. Clear, modular assertions make failures immediately understandable, particularly in larger testbenches, which aligns well with style-aware analysis tools. Issue 1: Functional Correctness A common misstep is to combine multiple signals in a single $isunknown call with a logical AND: // INCORRECT $isunknown(spiclk && mosi && miso) The problem: logical AND short-circuits evaluation, potentially masking unknown states. Example: spiclk = X, mosi = 0, miso = 1 spiclk ...