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BenchBot: Automating OSVVM-based VHDL Testbenches BenchBot is a Python-based automation tool designed to generate testbench templates based on OSVVM (Open Source VHDL Verification Methodology) for VHDL testbenches. This tool is particularly useful in hardware verification for FPGA and ASIC designs. Below is a technical breakdown of BenchBot. Core Functionality At its core, BenchBot processes a YAML file containing DUT (Device Under Test) specifications, automating the creation of VHDL testbench components. This includes not only the entity and architecture for the testbench but also the DUT’s port declarations and integration within the generated testbench. Key Features Testbench Generation : Automatically creates a complete testbench structure, including both the entity and architecture necessary for simulation. DUT Integration : Parses DUT ports from the input YAML and generates corresponding port declarations, followed by ac...

In VHDL-based digital design, ensuring that every key aspect of your design is tested comprehensively is critical. Functional coverage plays a pivotal role in this process by quantifying how thoroughly the testbench exercises the design's functionality. In this article, we will demonstrate how to create a functional coverage model for a simple up/down counter ( af_up_dn_counter ) using BenchBot, a Python tool for generating templated testbenches, in conjunction with OSVVM (Open Source VHDL Verification Methodology), which provides a robust functional coverage package. Setting Up the Testbench with BenchBot BenchBot, a Python app simplifies the creation of VHDL testbenches by generating template files.  It serves as a starting point rather than a fully functional testbench with all tests. However, it goes way beyond basic testbench by creating functional coverage model for all relevant DUT ports.  We will show an example of this below. Overview of the Design The design ...

 If you use VHDL to design FPGA or ASIC (RTL design), it is likely that you have come across OSVVM - a methodology library and collateral that can significantly enhance productivity of VHDL testbenches. While there are quite a few conference papers and articles on OSVVM internals, here is our humble attempt to use it on a small design - ground-up. This is not a full-fledged demo of all OSVVM capabilities, rather a beginner's guide to the wonderful world of design verification with OSVVM.  Before we go deeper into OSVVM, let's capture some common, protocol agnostic capabilities/features that every testbench would require:  Clock generation, with bells and whistles to enable/disable etc. Reset generation - with polarity control. Scalable and flexible messaging features - to print progress during a running simulation and also being able to control it on a regression later in the game. Watchdog - to alert those run-away simulations.  Clear separation from TestBench (TB) ...