Beyond the Hype: Moving AI-Driven Chip Design from "Cool Demo" to Production Grade

The "AI in EDA" conversation is currently dominated by two extremes: the hype of autonomous agents and the reality of legacy verification constraints.

While AI can generate code in seconds, the friction begins the moment that code hits a verification environment. Whether it’s the cost of commercial licenses or the risk of unvetted UVM sequences, the gap between a "cool demo" and a Production-Ready flow is wider than most realize.

At DVCon 2026, AsFigo is bridging that gap.

We are hosting a Birds of a Feather (BoF) session to look at the full stack of Silicon-Ready AI. We’ve assembled a panel of industry veterans and disruptors to examine how we actually scale:

  • The Workforce Shift: How global Centers of Excellence are integrating AI into existing UVM teams.
  • The Agentic Loop: Startup founders on building autonomous verification cycles that actually close coverage.
  • The Infrastructure: Solving the bottleneck of simulation licenses and specialized engines.
  • The Training Evolution: A veteran D&V trainer joins us to discuss how open-source engines are finally making high-level SVA and UVM learning accessible to everyone, for free.

The AsFigo Mission

At AsFigo, we provide the "Nervous System" for this transition. For AI to work in DV, it needs a sandbox that is fast, secure, and—most importantly—compatible with production standards.

Stay Tuned. Over the next 10 days, we will be releasing a series of updates on how we are unblocking the stack, including:

  • The "License Tax": A pragmatic approach to scaling AI-DV using hybrid flows.
  • The "Engine": How we reached the milestone of 50+ production-grade UVCs on Verilator.
  • The Guardrails: Using SVALint and UVMLint to vet AI-generated code.

See you at the BoF. The era of "toys" is over.

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