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BenchBot: Automating OSVVM-based VHDL Testbenches BenchBot is a Python-based automation tool designed to generate testbench templates based on OSVVM (Open Source VHDL Verification Methodology) for VHDL testbenches. This tool is particularly useful in hardware verification for FPGA and ASIC designs. Below is a technical breakdown of BenchBot. Core Functionality At its core, BenchBot processes a YAML file containing DUT (Device Under Test) specifications, automating the creation of VHDL testbench components. This includes not only the entity and architecture for the testbench but also the DUT’s port declarations and integration within the generated testbench. Key Features Testbench Generation : Automatically creates a complete testbench structure, including both the entity and architecture necessary for simulation. DUT Integration : Parses DUT ports from the input YAML and generates corresponding port declarations, followed by ac...

In VHDL-based digital design, ensuring that every key aspect of your design is tested comprehensively is critical. Functional coverage plays a pivotal role in this process by quantifying how thoroughly the testbench exercises the design's functionality. In this article, we will demonstrate how to create a functional coverage model for a simple up/down counter ( af_up_dn_counter ) using BenchBot, a Python tool for generating templated testbenches, in conjunction with OSVVM (Open Source VHDL Verification Methodology), which provides a robust functional coverage package. Setting Up the Testbench with BenchBot BenchBot, a Python app simplifies the creation of VHDL testbenches by generating template files.  It serves as a starting point rather than a fully functional testbench with all tests. However, it goes way beyond basic testbench by creating functional coverage model for all relevant DUT ports.  We will show an example of this below. Overview of the Design The design ...

 YAML, which stands for "YAML Ain't Markup Language," is a human-readable data serialization standard that is ideal for configuration files. We at AsFigo are helping customers adopt YAML for documenting VHDL (VHSIC Hardware Description Language) designs, especially at the interface level. One of the primary benefits of using YAML for VHDL designs is that it makes the information easier to parse and modify. This structured format allows for straightforward code generation and updates, significantly improving workflow efficiency. With YAML, you can create an organized, easy-to-read representation of VHDL entity interfaces, detailing ports, libraries, and other configurations. This structured approach not only aids developers in understanding and managing complex designs but also facilitates tool integration.   Below is a simple example YAML for a trivial up-down counter: Take a look at our opensource OSVVM Testbench generator project that utilizes this idea at: https://gith...

We at AsFigo AsFigo love Opensource. Off late we have been helping some European customers adopt modern verification techniques using VHDL. As a byproduct we have been building a Python based VHDL utility to generate a generic testbench based on OSVVM. While doing so, our team stumbled upon few subtle simulator issues, see: https://osvvm.org/forums/topic/sbrd-package-issue-with-modelsim-fpga-edition Hence, we wanted to try out NVC - a relatively new opensource VHDL compiler (https://www.nickg.me.uk/nvc/index.html). While there are pre-built binaries for several OS there, we couldn't locate one for WSL - Windows + WSL running Ubuntu. So, we decided to build it from source - isn't it the best thing about opensource - build missing pieces yourself?   So here is an Engineer's diary of how we got it up and running in less than 15 minutes! Fasten your seatbelt, off we go!  Follow the below steps: Grab the latest NVC tar ball from:  https://github.com/nickg/nvc/releases/ ....

VHDL holds a prominent position in the world of FPGA design, particularly within the military, aerospace, and defense sectors. It serves both as a Register Transfer Level (RTL) design language and as a tool for creating testbenches. The availability of open-source simulators, such as GHDL and NVC, alongside numerous free FPGA simulators and synthesis tools, has provided FPGA designers with a significant advantage over their SystemVerilog counterparts. While the Universal Verification Methodology (UVM) is widely adopted among SystemVerilog users, VHDL practitioners have traditionally relied on various homegrown methodologies and frameworks. Recently, however, off-the-shelf methodologies and frameworks such as OSVVM, UVVM, and VUnit have become available to VHDL users. Each of these options presents different levels of complexity, allowing users to choose the one that best meets their needs. Despite these advancements, the development of open-source utility tools supporting the latest me...

 If you use VHDL to design FPGA or ASIC (RTL design), it is likely that you have come across OSVVM - a methodology library and collateral that can significantly enhance productivity of VHDL testbenches. While there are quite a few conference papers and articles on OSVVM internals, here is our humble attempt to use it on a small design - ground-up. This is not a full-fledged demo of all OSVVM capabilities, rather a beginner's guide to the wonderful world of design verification with OSVVM.  Before we go deeper into OSVVM, let's capture some common, protocol agnostic capabilities/features that every testbench would require:  Clock generation, with bells and whistles to enable/disable etc. Reset generation - with polarity control. Scalable and flexible messaging features - to print progress during a running simulation and also being able to control it on a regression later in the game. Watchdog - to alert those run-away simulations.  Clear separation from TestBench (TB) ...