Solving the $100k License Tax: A Convergence of Industry Perspectives on Agentic AI for chip design

In our previous post, we discussed the gap between AI "demos" and production-grade silicon. Today, we address the primary friction point preventing the industry from scaling AI-driven verification: The License Tax.

The Math of Iteration

"Agentic AI"—where autonomous loops generate, test, and fix RTL—relies on high-frequency iteration. For an AI agent to "learn" a fix or optimize a module, it may need to run hundreds or thousands of cycles through a verification engine.

In a traditional environment, this is an economic impossibility. If every iterative trial pings a commercial tool seat—often costing upwards of $100,000 per license—the cost of the "agentic workforce" scales faster than its productivity. To make AI ROI viable, we must decouple the high-volume iterative cleaning from the high-cost final sign-off.

The Production Milestone: Verilator + UVM is becoming a reality. AsFigo and VerifWorks have already ported 50+ production-grade UVCs to Verilator. While these currently support the first few tests with documented limitations and workarounds, they represent a functional "Utility" layer that was previously unavailable for high-frequency AI iteration.

Building the Guardrails

The solution lies in a hybrid flow. At AsFigo Technologies, we’ve focused on building the "Ground Truth" necessary for these AI agents to operate safely and affordably. By utilizing open-source engines like Verilator and Slang, we provide a low-overhead sandbox for AI agents to iterate.

Crucially, this iteration is governed by specific guardrails such as SVALint and UVMLint. These tools, built on top of Google Verible and Slang, act as the gatekeepers—ensuring that AI-generated code meets rigid industrial standards before it is ever promoted to a commercial simulator.

A Convergence of Industry Perspectives

This isn’t a theoretical shift; it’s a practical necessity being addressed by a diverse group of industry veterans and innovators. We are hosting a private co-located meeting during the week of DVCon U.S. 2026 to explore how this stack is being viewed and deployed across the following perspectives:

  • Deepak Tala (SmartDV): The commercial reality of maintaining high-revenue IP quality in an evolving tool landscape.
  • Shashank Chaurasia (MooresLabAI): Real-world implementation of "tool-in-the-loop" agents within a VC-backed startup pipeline.
  • Akash Levy (Silimate): Exploring "AI-Native" flows for real-time PPA and functional feedback in VC-backed innovation.
  • Clifford Cummings (Sunburst Design): A veteran "Guru" perspective on the talent pipeline and expert education in an open-source world.
  • Yatin Trivedi (Capgemini): The enterprise view on managing mass AI deployment and risk for global design service teams.
  • Asif ETV (HPC Infra): The architectural requirements for secure, professional-grade infrastructure in the enterprise AI era.

Event Logistics

This is an independent, private event hosted by AsFigo Technologies and co-located with the conference. To ensure a focused technical environment, registration is mandatory, though the session is free for attendees.

Location: Ballroom C, Hyatt Regency, Santa Clara, CA
When: Monday, March 2nd, 2026 | 6:00 PM – 7:00 PM PST
Registration: [Link to be added]

Comments

Post a Comment

Popular posts from this blog

Join Us in Cambridge - Advancing Chip Verification with UVMLint & SVALint

AsFigo invites you to our next technical session, focused on enabling semiconductor design teams to adopt open-source EDA tools—especially for testbench linting workflows. Remote-dial-in link:  UVMLint meetup - Cambridge, June 27 | Meeting-Join | Microsoft Teams 📍 Event: UVMLint & SVALint – Enablers to Move Your Chip Design Ahead 📅 Date: Friday, June 27, 2025 🕙 Time: 10:00 AM to 12:00 Noon (UK Time) 📌 Location: Wellington House, East Road, Cambridge, CB1 1BH, United Kingdom ☎ Phone: +44 1223 451000 🌐 Format: Hybrid (in-person & remote via Microsoft Teams) 💡 Cost: Free (registration required - https://forms.gle/upzLGyWJbRnbgRzU7 ) After a successful SVALint session in Reading, UK, we’re bringing this discussion to Cambridge—one of the UK’s most active semiconductor hubs. This event is geared toward engineers working in UVM based verification, formal verification, and testbench architecture using UVM and SVA. Ag...
Read more

SVALint Technical Meetup – Reading, UK

SVALint Technical Meetup – Hybrid Event in Reading, UK AsFigo invites engineers and verification professionals to a focused technical meetup on SVALint —an open-source static verification abstraction linting framework. The event takes place on Sunday, 8 June 2025 , from 15:00 to 18:00 BST , hosted in a hybrid format (face-to-face and online). Register via:  https://forms.gle/qo8TBczXjNk62yAP6   Venue (In-Person) Meeting Room-5, First floor,  Novotel Reading Centre 25B Friar Street – RG1 1DP, Reading – United Kingdom T +44 (0) 1189 522 610 novotel.com/5432 Virtual Attendance Join via Microsoft Teams Why SVA Linting? SystemVerilog Assertions (SVA) play a critical role in ensuring correctness in complex verification environments. However, poorly structured assertions can hurt simulation performance, complicate debugging, or lead to ambiguous semantics. Linting SVAs helps catch such issues early—enforci...
Read more

Call for Collaboration: Seeking Public UVM Environments for Verilator 5.0+ Porting

The transition of SystemVerilog UVM environments to open-source simulators presents specific technical challenges. While Verilator 5.0+ has expanded support for various SystemVerilog constructs, the industry still lacks a documented and repeatable path for certain UVM-specific behaviors. In parallel, we aim to curate a public vault of UVM repositories that have been successfully ported to Verilator. AsFigo is initiating a collaborative effort to document these gaps, and we are looking for engineers, researchers, and students to contribute original UVM codebases to this effort.  Link to Google Form: Submit Your code base The Technical Focus This effort intentionally moves beyond minimal or illustrative examples. We are seeking unique, original UVM implementations that reflect realistic UVM environments and non-trivial SystemVerilog usage found in real-world verification flows. Infrastructure Components: Memo...
Read more