AsFigo - enabling opensource chip design and verification.

Back in 2023, we started building open-source lint tools for the parts of SystemVerilog that commercial linters tend to treat as an afterthought — assertions, constraint blocks, and functional coverage. What began as a handful of rules has grown into a substantial rule set: SVALint , CNSTLint , and FCOVLint now collectively cover over 90 lint rules, all built on the Verible parser and the BYOL (Build Your Own Linter) framework. This post highlights the rules that catch real bugs, silent misbehaviour, and tool-specific pitfalls — not naming conventions. Full rationale, violation examples, and correct usage are in the linked docs. SVALint — Assertion Linting (52 rules) Repo: github.com/AsFigo/svalint  |  Docs: asfigo.github.io/svalint/ SVA is deceptively easy to write incorrectly. These rules catch issues that compile cleanly, pass elaboration, and then silently misbehave in simulation or formal verification. Rule ID Bug it catches DELAY_BEFORE_ROSE D...

AsFigo is organising a 3-hour hybrid bootcamp on open-source chip design and verification in Bengaluru on Monday, 31 August 2026, immediately ahead of DVCon India 2026. Date: Monday, 31 August 2026 Time: 1:00–4:00 PM IST Location: Bengaluru, ORR / Bellandur area — venue to be confirmed Format: Hybrid Cost: Free to attend Registration: Required The event brings together a deliberately diverse set of open-source verification projects and approaches — from UVM and Verilator to Rust-based verification, formal, functional-coverage linting, OSVVM and SystemVerilog Assertions. The aim is not to promote one particular tool or methodology. It is to bring together people working on different parts of the ecosystem and explore what is becoming possible with open-source verification. A journey that started well before this event AsFigo's work in open-source verification builds on a much longer history in design verification. Our founders, Ajeetha Kumari and Srinivasan Venkataramanan, ha...

Join AsFigo—trailblazers in open-source SVA, UVM Lint, and simulation workflows since 2023—for an exclusive San Diego meetup where we will unpack the next era of semiconductor innovation. MS Teams link:  https://teams.microsoft.com/meet/39182483503977?p=BgU2EhioUoKoNVfOfR   Date: Thursday, July 30, 2026 Time: 5:30 PM – 7:30 PM (PDT) Location: Capital One Café - San Diego (Community Room 1) | 4311 La Jolla Village Drive, San Diego, CA, 92122 Format: Hybrid (In-Person & Virtual via MS Teams) Hosted By: AsFigo (UK) Cost: Free (Registration Mandatory) The Next Wave of Semiconductor Innovation The semiconductor landscape is undergoing a massive paradigm shift. As hardware complexity skyrockets, traditional Electronic Design Automation (EDA) workflows are meeting their match. Enter open-source EDA and artificial intelligence —a powerful combination that is tearing down barriers, accelerating innovation, and transforming how...

As we gear up for the 63rd Design Automation Conference (DAC) next week, the engineering team at AsFigo (in collaboration with VerifWorks) is rolling out a major extension to SVALint —our blazing-fast, Verible-backed SystemVerilog Assertion linter. Among our new suite of functional correctness checks, one major hazard we are targeting is the misapplication of liveness operators in dynamic simulation environments: specifically, bounded weak-strong patterns like eventually s_always . The Trap: A Common Scenario with pll_locked Consider a standard verification check for a clock generation block. An engineer writes an assertion expecting that within a reasonable window after reset, the PLL locks and remains permanently stable: // Risky Assertion Style property p_pll_stable; @(posedge clk) disable iff (!rst_n) eventually [1:10] always pll_locked; endproperty : p_pll_stable a_p_pll_stable : assert property (p_pll_stable) else begin `uvm_error("a_p_pll_s...

At AsFigo , we have always believed that the best verification tools grow organically from real engineering friction. Over the last couple of years, as AI coding assistants have flooded into hardware workflows, that friction has fundamentally shifted. The core bottleneck is no longer just writing code—it is safely and predictably integrating AI-generated code into complex, existing environments. As a small but dedicated contributor to the open-source EDA community, we want to share the journey of how SVALint evolved from a localized parser experiment into an essential guardrail for modern AI-assisted verification. From Experiment to Ecosystem: The SVALint Journey Our work on SVALint began in early 2023, we began experimenting with the early stages of slang and PySlang . That work led to PySlint , and eventually, we built out a custom linting infrastructure specifically focused on SystemVerilog testbench (including SVA). We took those early iterations to the community, gatheri...

This first installment of our DVCon US ’26 video series dives straight into a reality check that often gets lost in the hype of generative AI: The cost of a single "thought." In this segment, Srini (AsFigo) sits down with Asif ETV (HPCINFRA) to discuss why the transition to AI-native chip design isn't just a software challenge—it’s a massive infrastructure and economic hurdle. Watch the Full Segment :  In this 3-minute clip, watch Asif and Srini break down the economic reality of the modern AI-EDA stack and why optimizing for the right infrastructure is the only way to stay within budget while bringing AI into production. The Cost Explosion: Doing the Math on Hallucinations When we talk about "Agentic AI" in EDA, we imagine autonomous loops of design and verification. But as Asif ETV points out, the meter is always running, and it’s running faster than many teams realize. Sharing a startling metric from recent infrastructure experiments, the m...

Ensuring Correctness and Observability in SPI Signal Assertions In SPI verification, a fundamental requirement is that all active signals— SCLK , MOSI , and MISO —must be fully defined whenever chip-select is asserted . Any unknown or high-impedance state ( X or Z ) can compromise data integrity and lead to subtle bugs. SystemVerilog Assertions (SVA) offer a natural mechanism to codify this requirement. When applied thoughtfully, they enforce correctness and enhance diagnostic clarity. Clear, modular assertions make failures immediately understandable, particularly in larger testbenches, which aligns well with style-aware analysis tools. Issue 1: Functional Correctness A common misstep is to combine multiple signals in a single $isunknown call with a logical AND: // INCORRECT $isunknown(spiclk && mosi && miso) The problem: logical AND short-circuits evaluation, potentially masking unknown states. Example: spiclk = X, mosi = 0, miso = 1 spiclk ...

We're inviting all SystemVerilog developers to share their testbench code using #UVM and/or #SVA for a free lint-check as part of our upcoming technical meetup. ✅ Submit your repo path or URL ✅ We’ll run our lint tools on it ✅ Get a detailed report ✅ Your code might be featured in a live demo! 🗓️ Event: #UVMLint and #SVALint Meetup 📍 Location: Cambridge, UK (remote attendance available) 👥 113+ engineers already registered , and counting! Don’t miss the chance to get valuable insights into your testbench quality — from syntax to assertions to methodology compliance. Register now: https://lnkd.in/dW3nX_KC Join via:  UVMLint meetup - Cambridge, June 27 | Meeting-Join | Microsoft Teams   Special thanks to our collaborators: Ajeetha Kumari, Ben Cohen, Hemamalini Sundaram and the #AsFigo team. #SystemVerilog #UVM #SVA #Lint #EDA #Verification #OpenSource #Meetup

AsFigo invites you to our next technical session, focused on enabling semiconductor design teams to adopt open-source EDA tools—especially for testbench linting workflows. Remote-dial-in link:  UVMLint meetup - Cambridge, June 27 | Meeting-Join | Microsoft Teams 📍 Event: UVMLint & SVALint – Enablers to Move Your Chip Design Ahead 📅 Date: Friday, June 27, 2025 🕙 Time: 10:00 AM to 12:00 Noon (UK Time) 📌 Location: Wellington House, East Road, Cambridge, CB1 1BH, United Kingdom ☎ Phone: +44 1223 451000 🌐 Format: Hybrid (in-person & remote via Microsoft Teams) 💡 Cost: Free (registration required - https://forms.gle/upzLGyWJbRnbgRzU7 ) After a successful SVALint session in Reading, UK, we’re bringing this discussion to Cambridge—one of the UK’s most active semiconductor hubs. This event is geared toward engineers working in UVM based verification, formal verification, and testbench architecture using UVM and SVA. Ag...

SVALint Technical Meetup – Hybrid Event in Reading, UK AsFigo invites engineers and verification professionals to a focused technical meetup on SVALint —an open-source static verification abstraction linting framework. The event takes place on Sunday, 8 June 2025 , from 15:00 to 18:00 BST , hosted in a hybrid format (face-to-face and online). Register via:  https://forms.gle/qo8TBczXjNk62yAP6   Venue (In-Person) Meeting Room-5, First floor,  Novotel Reading Centre 25B Friar Street – RG1 1DP, Reading – United Kingdom T +44 (0) 1189 522 610 novotel.com/5432 Virtual Attendance Join via Microsoft Teams Why SVA Linting? SystemVerilog Assertions (SVA) play a critical role in ensuring correctness in complex verification environments. However, poorly structured assertions can hurt simulation performance, complicate debugging, or lead to ambiguous semantics. Linting SVAs helps catch such issues early—enforci...