AsFigo - enabling opensource chip design and verification.

This first installment of our DVCon US ’26 video series dives straight into a reality check that often gets lost in the hype of generative AI: The cost of a single "thought." In this segment, Srini (AsFigo) sits down with Asif ETV (HPCINFRA) to discuss why the transition to AI-native chip design isn't just a software challenge—it’s a massive infrastructure and economic hurdle. Watch the Full Segment :  In this 3-minute clip, watch Asif and Srini break down the economic reality of the modern AI-EDA stack and why optimizing for the right infrastructure is the only way to stay within budget while bringing AI into production. The Cost Explosion: Doing the Math on Hallucinations When we talk about "Agentic AI" in EDA, we imagine autonomous loops of design and verification. But as Asif ETV points out, the meter is always running, and it’s running faster than many teams realize. Sharing a startling metric from recent infrastructure experiments, the m...

Ensuring Correctness and Observability in SPI Signal Assertions In SPI verification, a fundamental requirement is that all active signals— SCLK , MOSI , and MISO —must be fully defined whenever chip-select is asserted . Any unknown or high-impedance state ( X or Z ) can compromise data integrity and lead to subtle bugs. SystemVerilog Assertions (SVA) offer a natural mechanism to codify this requirement. When applied thoughtfully, they enforce correctness and enhance diagnostic clarity. Clear, modular assertions make failures immediately understandable, particularly in larger testbenches, which aligns well with style-aware analysis tools. Issue 1: Functional Correctness A common misstep is to combine multiple signals in a single $isunknown call with a logical AND: // INCORRECT $isunknown(spiclk && mosi && miso) The problem: logical AND short-circuits evaluation, potentially masking unknown states. Example: spiclk = X, mosi = 0, miso = 1 spiclk ...

We're inviting all SystemVerilog developers to share their testbench code using #UVM and/or #SVA for a free lint-check as part of our upcoming technical meetup. ✅ Submit your repo path or URL ✅ We’ll run our lint tools on it ✅ Get a detailed report ✅ Your code might be featured in a live demo! 🗓️ Event: #UVMLint and #SVALint Meetup 📍 Location: Cambridge, UK (remote attendance available) 👥 113+ engineers already registered , and counting! Don’t miss the chance to get valuable insights into your testbench quality — from syntax to assertions to methodology compliance. Register now: https://lnkd.in/dW3nX_KC Join via:  UVMLint meetup - Cambridge, June 27 | Meeting-Join | Microsoft Teams   Special thanks to our collaborators: Ajeetha Kumari, Ben Cohen, Hemamalini Sundaram and the #AsFigo team. #SystemVerilog #UVM #SVA #Lint #EDA #Verification #OpenSource #Meetup

AsFigo invites you to our next technical session, focused on enabling semiconductor design teams to adopt open-source EDA tools—especially for testbench linting workflows. Remote-dial-in link:  UVMLint meetup - Cambridge, June 27 | Meeting-Join | Microsoft Teams 📍 Event: UVMLint & SVALint – Enablers to Move Your Chip Design Ahead 📅 Date: Friday, June 27, 2025 🕙 Time: 10:00 AM to 12:00 Noon (UK Time) 📌 Location: Wellington House, East Road, Cambridge, CB1 1BH, United Kingdom ☎ Phone: +44 1223 451000 🌐 Format: Hybrid (in-person & remote via Microsoft Teams) 💡 Cost: Free (registration required - https://forms.gle/upzLGyWJbRnbgRzU7 ) After a successful SVALint session in Reading, UK, we’re bringing this discussion to Cambridge—one of the UK’s most active semiconductor hubs. This event is geared toward engineers working in UVM based verification, formal verification, and testbench architecture using UVM and SVA. Ag...

SVALint Technical Meetup – Hybrid Event in Reading, UK AsFigo invites engineers and verification professionals to a focused technical meetup on SVALint —an open-source static verification abstraction linting framework. The event takes place on Sunday, 8 June 2025 , from 15:00 to 18:00 BST , hosted in a hybrid format (face-to-face and online). Register via:  https://forms.gle/qo8TBczXjNk62yAP6   Venue (In-Person) Meeting Room-5, First floor,  Novotel Reading Centre 25B Friar Street – RG1 1DP, Reading – United Kingdom T +44 (0) 1189 522 610 novotel.com/5432 Virtual Attendance Join via Microsoft Teams Why SVA Linting? SystemVerilog Assertions (SVA) play a critical role in ensuring correctness in complex verification environments. However, poorly structured assertions can hurt simulation performance, complicate debugging, or lead to ambiguous semantics. Linting SVAs helps catch such issues early—enforci...