Cracking the UVM-Verilator Code: 50+ IPs, AI Guardrails, and the Open-Source North Star

UVM on Verilator Isn’t Impossible. It’s Just Hard. We Did It Anyway.

The “standard” line in the industry:

  • UVM and Verilator don’t mix.
  • Enterprise-grade open-source verification is a fantasy.

So we put that claim under load.

  • ✔ 50+ production UVCs ported
  • ✔ 35+ non-obvious failure modes uncovered
  • ✔ Converted into UVMLint and SVALint rules
  • ✔ AI guardrails to prevent regressions

This post is the why and what; the how and numbers are for the room at Hacker Dojo. 

This is production-grade code—the kind that tapes out chips—running on open-source infrastructure.

The implication is bigger than a port:

  1. Reduced dependency on closed ecosystems.
  2. Negotiating leverage with EDA vendors.
  3. Strategic control over your verification stack.

If you’re a semiconductor company exploring Verilator for serious IP, don’t start from scratch. Start from the team that already mapped the minefield.

📅 Join us at the Hacker Dojo

Next Thursday, the AsFigo team and our partners will be live in Mountain View to present the data, the infrastructure, and the roadmap behind these results.

  • When: Next Thursday, March 5th, 2026, 4–6 PM PST
  • Where: Hacker Dojo, Mountain View, CA (and streaming live)
  • Who: Verification engineers, hardware founders, and open-source advocates.

📋 The Agenda

1. The Engine: Porting 50+ Production UVCs to Verilator

We will unpack results from 50+ real-world UVCs executed on a custom Verilator BCL — demonstrating that open-source simulator can sustain enterprise verification demands without abandoning standard UVM methodology.

The gap between “possible” and “production-ready” just closed.

2. The Guardrails: Deterministic AI for UVM

Speaker: Ajeetha Kumari (Director of Verification, AsFigo)

From porting 50+ production UVCs, we didn’t just learn what breaks — we codified it.

Those 35+ syntatic and semantic gotchas are no longer tribal knowledge. They’re embedded into SVALint and UVMLint — and now serve as the deterministic backbone of our agentic AI verification flow.

As LLMs enter hardware design, hallucination risk is unacceptable. Ajeetha  will demonstrate how we layer AI generation with rule-based enforcement — ensuring every AI-produced artifact is validated against production-proven constraints.

In short:

  • AI accelerates.
  • Lint enforces.
  • Tape-outs stay safe.

3. The Cloud-Native Compile: AWS Economics for Verilator

Speaker: AsFigo Team (Under the guidance of Isaar Ahmad, Univ. of Bristol)

Verilator is blazingly fast at runtime, but UVM elaboration can hit a massive C++ RAM wall. We will present exclusive data mapping the exact AWS price-to-performance compute floor for global-scale verification.

4. The Python Production Alternative: AVL

Speaker: Andrew Bond — Not every verification engineer wants to live in SystemVerilog.

Andrew Bond, Director of Verification at Axelera AI, will showcase AVL in action — demonstrating how production-grade hardware verification for cutting-edge AI accelerators can be built efficiently in Python.

Modern chips. Modern flows. Modern languages.

5. From Code to Silicon: RTL Design, SV, and Synthesis

Speaker: Yuri

In a 15-minute power preview, Yuri bridges the gap between design and silicon. He will showcase how Verilator is leveraged for RTL design and how Yosys is used for open-source synthesis. Yuri will also provide a preview of his SNUG paper, anchoring these developments to the industry's highest standards.

The North Star: A License-Free Ecosystem

Our 6-month roadmap targets the world's most critical open-source silicon—from Ibex and CV32 cores to complete OpenTitan subsystems—running entirely on Verilator.

[RSVP Link Here] to join us next Thursday.

(Note: For the engineers wanting the heavy technical details, keep an eye out for Part 2 of this blog series, where we will deep-dive into the top Verilator UVM "gotchas"—from solving the dreaded Time-0 OBJTN_CLEAR trap to cleaning up UVM 1.1d legacy baggage.)

Comments

Post a Comment

Popular posts from this blog

Join Us in Cambridge - Advancing Chip Verification with UVMLint & SVALint

AsFigo invites you to our next technical session, focused on enabling semiconductor design teams to adopt open-source EDA tools—especially for testbench linting workflows. Remote-dial-in link:  UVMLint meetup - Cambridge, June 27 | Meeting-Join | Microsoft Teams 📍 Event: UVMLint & SVALint – Enablers to Move Your Chip Design Ahead 📅 Date: Friday, June 27, 2025 🕙 Time: 10:00 AM to 12:00 Noon (UK Time) 📌 Location: Wellington House, East Road, Cambridge, CB1 1BH, United Kingdom ☎ Phone: +44 1223 451000 🌐 Format: Hybrid (in-person & remote via Microsoft Teams) 💡 Cost: Free (registration required - https://forms.gle/upzLGyWJbRnbgRzU7 ) After a successful SVALint session in Reading, UK, we’re bringing this discussion to Cambridge—one of the UK’s most active semiconductor hubs. This event is geared toward engineers working in UVM based verification, formal verification, and testbench architecture using UVM and SVA. Ag...
Read more

SVALint Technical Meetup – Reading, UK

SVALint Technical Meetup – Hybrid Event in Reading, UK AsFigo invites engineers and verification professionals to a focused technical meetup on SVALint —an open-source static verification abstraction linting framework. The event takes place on Sunday, 8 June 2025 , from 15:00 to 18:00 BST , hosted in a hybrid format (face-to-face and online). Register via:  https://forms.gle/qo8TBczXjNk62yAP6   Venue (In-Person) Meeting Room-5, First floor,  Novotel Reading Centre 25B Friar Street – RG1 1DP, Reading – United Kingdom T +44 (0) 1189 522 610 novotel.com/5432 Virtual Attendance Join via Microsoft Teams Why SVA Linting? SystemVerilog Assertions (SVA) play a critical role in ensuring correctness in complex verification environments. However, poorly structured assertions can hurt simulation performance, complicate debugging, or lead to ambiguous semantics. Linting SVAs helps catch such issues early—enforci...
Read more

Call for Collaboration: Seeking Public UVM Environments for Verilator 5.0+ Porting

The transition of SystemVerilog UVM environments to open-source simulators presents specific technical challenges. While Verilator 5.0+ has expanded support for various SystemVerilog constructs, the industry still lacks a documented and repeatable path for certain UVM-specific behaviors. In parallel, we aim to curate a public vault of UVM repositories that have been successfully ported to Verilator. AsFigo is initiating a collaborative effort to document these gaps, and we are looking for engineers, researchers, and students to contribute original UVM codebases to this effort.  Link to Google Form: Submit Your code base The Technical Focus This effort intentionally moves beyond minimal or illustrative examples. We are seeking unique, original UVM implementations that reflect realistic UVM environments and non-trivial SystemVerilog usage found in real-world verification flows. Infrastructure Components: Memo...
Read more