Opensource Bootcamp Update: OSVVM Joins the Lineup, Keynote Confirmed, Agenda Extended

A few updates since our first announcement for the Open-Source Chip Design & Verification Bootcamp (31 Aug 2026, BHIVE Bellandur, Bengaluru + Hybrid):

REGISTER NOW - https://tinyurl.com/asfigoblr26  


Keynote confirmed: Satish Sridharan, Sr. Director Digital, Aura Semiconductor

New speaker added: Jim Lewis, chief architect of OSVVM, presenting "OSVVM: A Better Way to Verify Your VHDL Designs"

New talk added: CNSTLint (constraint linting) by Nambi JU

Agenda extended to 5:30 PM for more depth and Q&A across sessions

Full lineup:

Updated Agenda — Monday, 31 August 2026 | 1:00 PM – 5:30 PM IST
BHIVE Premium Bellandur Campus, Bengaluru (Hybrid)

Time (IST) Session Speaker Mode
1:00 – 1:10 PM Welcome & Intro Srinivasan Venkataramanan, AsFigo In-person
1:10 – 1:25 PM Keynote Satish Sridharan, Sr. Director Digital, Aura Semiconductor In-person
1:30 – 2:15 PM RustDV — The UVM in Rust Ray Salemi Recording
2:20 – 2:40 PM CNSTLint — Constraint Linting Nambi JU In-person
2:45 – 3:05 PM Kepler-Formal Noam Cohen, Kepler Tech Remote (France)
3:10 – 3:30 PM FCOVLint — Functional Coverage Linting Sridevi Darapureddi, VerifWorks In-person
3:35 – 4:00 PM PyUVM — Making pyuvm Usable for Industrial Verification Yogish Sekhar In-person
4:05 – 4:25 PM SVALint — SVA Linting Manohar Natarajan, SiSethu In-person
4:30 – 5:00 PM OSVVM — A Better Way to Verify Your VHDL Designs Jim Lewis Remote (US)
5:00 – 5:30 PM Wrap-up & Networking Ramakrishnan K / Srinivasan Venkataramanan In-person

Monday, 31 August 2026 | 1:00–5:30 PM IST | Hybrid

Full agenda: see updated schedule here
Free to attend — registration required.

REGISTER NOW - https://tinyurl.com/asfigoblr26  


Comments

Post a Comment

Popular posts from this blog

Cracking the UVM-Verilator Code: 50+ IPs, AI Guardrails, and the Open-Source North Star

UVM on Verilator Isn’t Impossible. It’s Just Hard. We Did It Anyway. The “standard” line in the industry: UVM and Verilator don’t mix. Enterprise-grade open-source verification is a fantasy. So we put that claim under load. ✔ 50+ production UVCs ported ✔ 35 + non-obvious failure modes uncovered ✔ Converted into UVMLint and SVALint rules ✔ AI guardrails to prevent regressions This post is the why and what; the how and numbers are for the room at Hacker Dojo.  This is production-grade code—the kind that tapes out chips—running on open-source infrastructure. The implication is bigger than a port: Reduced dependency on closed ecosystems. Negotiating leverage with EDA vendors. Strategic control over your verification stack. If you’re a semiconductor company exploring Verilator for serious IP, don’t start from scratch. Start from the team that already mapped the minefield. 📅 Join us at the Hacker Dojo Next Thursday, the AsFigo team...
Read more

Open-Source Chip Design & Verification Bootcamp — Programme & Speakers

Bengaluru | Monday, 31 August 2026 | 1:00–5:30 PM IST  | 8:30–13:00 BST (UK) | 9:30 AM–14:00 PM CEST (Central Europe) REGISTER NOW - https://tinyurl.com/asfigoblr26    Remote dial-in link:  AsFigo: Open-Source Chip Design & Verification Bootcamp | Meeting-Join | Microsoft Teams Following our earlier announcement, the programme and speakers for the AsFigo Open-Source Chip Design & Verification Bootcamp are now taking shape. For background and the story behind this event, see our earlier post . Event Details AsFigo invites working professionals, researchers, students and semiconductor enthusiasts to participate in this interactive technical meetup focused on open-source chip design and verification. Date: Monday, 31 August 2026 Time: 1:00–5:30 PM IST | 8:30 AM –13:00 PM BST (UK) | 9:30 AM–14:00 PM CEST (Central Europe) Format: Hybrid Host: AsFigo In-person: BHIVE Premium Bellandur Campus, Ratan Tata Conf room | Ground Floor; ...
Read more

Call for Collaboration: Seeking Public UVM Environments for Verilator 5.0+ Porting

The transition of SystemVerilog UVM environments to open-source simulators presents specific technical challenges. While Verilator 5.0+ has expanded support for various SystemVerilog constructs, the industry still lacks a documented and repeatable path for certain UVM-specific behaviors. In parallel, we aim to curate a public vault of UVM repositories that have been successfully ported to Verilator. AsFigo is initiating a collaborative effort to document these gaps, and we are looking for engineers, researchers, and students to contribute original UVM codebases to this effort.  Link to Google Form: Submit Your code base The Technical Focus This effort intentionally moves beyond minimal or illustrative examples. We are seeking unique, original UVM implementations that reflect realistic UVM environments and non-trivial SystemVerilog usage found in real-world verification flows. Infrastructure Components: Memo...
Read more