AsFigo - enabling opensource chip design and verification.

Back in 2023, we started building open-source lint tools for the parts of SystemVerilog that commercial linters tend to treat as an afterthought — assertions, constraint blocks, and functional coverage. What began as a handful of rules has grown into a substantial rule set: SVALint , CNSTLint , and FCOVLint now collectively cover over 90 lint rules, all built on the Verible parser and the BYOL (Build Your Own Linter) framework. This post highlights the rules that catch real bugs, silent misbehaviour, and tool-specific pitfalls — not naming conventions. Full rationale, violation examples, and correct usage are in the linked docs. SVALint — Assertion Linting (52 rules) Repo: github.com/AsFigo/svalint  |  Docs: asfigo.github.io/svalint/ SVA is deceptively easy to write incorrectly. These rules catch issues that compile cleanly, pass elaboration, and then silently misbehave in simulation or formal verification. Rule ID Bug it catches DELAY_BEFORE_ROSE D...

Why Regex Is the Wrong Abstraction for SystemVerilog Coverage Linting When building a lint rule for SystemVerilog functional coverage, it is tempting to start with a regular expression. The problem can initially appear simple: find array-based coverpoint bins, calculate how many bins they expand into, and report a violation if the count exceeds the supported limit. A first implementation might read the source file, remove comments, and search for patterns such as bins foo[] = {[0:2048]}; . As a first-cut implementation, this is perfectly reasonable. It is small, easy to prototype, and useful for validating the basic rule logic. The problem is that regular expressions operate on source text , while a lint rule needs to reason about language structure . Consider: bins values[] = { [0:2048], [3000:4000] }; The rule now needs to understand that this is one array-bin declaration containing multiple ranges, and calculate the expansion represented by those ranges. A re...