Open-Source Chip Design & Verification Bootcamp — Programme & Speakers

Bengaluru | Monday, 31 August 2026 | 1:00–5:30 PM IST  | 8:30–13:00 BST (UK) | 9:30 AM–14:00 PM CEST (Central Europe)

REGISTER NOW - https://tinyurl.com/asfigoblr26  


Following our earlier announcement, the programme and speakers for the AsFigo Open-Source Chip Design & Verification Bootcamp are now taking shape.

For background and the story behind this event, see our earlier post.

Event Details

AsFigo invites working professionals, researchers, students and semiconductor enthusiasts to participate in this interactive technical meetup focused on open-source chip design and verification.

REGISTER NOW - https://tinyurl.com/asfigoblr26 

Programme

Updated Agenda — Monday, 31 August 2026 | 1:00 PM – 5:30 PM IST

BHIVE Premium Bellandur Campus, Bengaluru (Hybrid)

Time (IST) Session Speaker Mode
1:00 – 1:10 PM Welcome & Intro Srinivasan Venkataramanan, AsFigo In-person
1:10 – 1:25 PM Keynote Satish Sridharan, Sr. Director Digital, Aura Semiconductor In-person
1:30 – 2:15 PM RustDV — The UVM in Rust Ray Salemi Recording
2:20 – 2:40 PM CNSTLint — Constraint Linting Nambi JU In-person
2:45 – 3:05 PM Kepler-Formal Noam Cohen, Kepler Tech Remote (France)
3:10 – 3:30 PM FCOVLint — Functional Coverage Linting Sridevi Darapureddi, VerifWorks In-person
3:35 – 4:00 PM PyUVM — Making pyuvm Usable for Industrial Verification Yogish Sekhar In-person
4:05 – 4:25 PM SVALint — SVA Linting Manohar Natarajan, SiSethu In-person
4:30 – 5:00 PM OSVVM — A Better Way to Verify Your VHDL Designs Jim Lewis Remote (US)
5:00 – 5:30 PM Wrap-up & Networking Rama / Srinivasan Venkataramanan In-person

Free to attend — registration required: https://tinyurl.com/asfigoblr26

Keynote - Satish Sridharan, Senior Director, Digital at Aura Semiconductor

Satish Sridharan is Senior Director of Digital at Aura Semiconductor, where he has led digital design efforts for over 14 years. He brings more than three decades of experience in semiconductors and ASIC design, having previously served as Senior Principal Engineer at Infinera (across its Los Angeles and Bangalore teams) and as a Member of Technical Staff at Vitesse Semiconductor. Satish has also spent time on the entrepreneurial side, as CEO of Ventura Pranas and co-founder of VecturaLux, and as CTO of IQC Advanced Inspection Solutions. He holds a B.Tech in Electronics and Communication Engineering from IIT Madras and an MS in Electrical and Computer Engineering from the University of Arizona.

RustDV — The UVM in Rust

Ray Salemi

An exploration of bringing the UVM methodology to Rust and what Rust-based verification can offer to the open-source verification ecosystem.

Abstract & Speaker Bio

Ray Salemi is a 30-year veteran of the high-tech industry, with experience leading engineering, customer support and sales teams. He is an expert verification engineer, consultant, author and the creator of pyUVM, bringing UVM concepts to Python. Ray has authored several books on verification, including The UVM Primer, Python for RTL Verification, and Rust for RTL Verification. His work spans SystemVerilog/UVM, Python, cocotb, pyUVM and now Rust-based RTL verification. He is also a teacher and continues to contribute to verification education and the open-source verification community.

Kepler-Formal

Noam Cohen

An introduction to Kepler-Formal and its approach to open-source formal verification.

Abstract & Speaker Bio

kepler formal is an open source formal verification tool targeting industrial grade designs. For a long time, one of the crucial items missing in the open silicon ecosystem has been formal verification solutions capable of verifying modern scale architectures. kepler formal provides exactly that, with an advanced multi threaded C++ core that can handle even large designs in a timely fashion. In this talk, we will present the tool and its use model, as well as our roadmap in terms of format support and features.

Noam Cohen is the Co-Founder and CTO of keplertech.io. Throughout his corporate career, he led R&D teams at SNPS and Siemens, dedicated to compiler development for hardware prototyping and emulation, with a focus on optimizing solutions to NP-hard problems such as partitioning, placement, and routing, and with an emphasis on high performance computing. After 10 years with the EDA industry leaders, he co-founded keplertech.io with the aim of introducing innovation in both technology and user experience to hardware design software tools.

FCOVLint


Functional-coverage linting aimed at identifying common coverage modelling issues before they become misleading or costly coverage results.

Abstract & Speaker Bio

Functional coverage is trusted as the record of what's been verified, but the constructs used to write it — covergroup, coverpoint, bins, cross — have a huge impact on verification that never show up as compile errors. A covergroup can compile cleanly and still be suboptimal:

  1. Consider: illegal_bins masking a real design bug instead of letting SVA or a scoreboard catch it;
  2. At a subsystem with multiple instances of the same IP, merge_instances hiding per-instance holes behind an aggregate that looks complete
  3. Huge performance degradation due to implicit edge-triggered sampling quietly running every clock cycle instead of at the transaction boundary.

These are methodology and performance bugs, not syntax errors, so nothing in the normal compile-and-simulate flow flags them.

FCOVLint is a static lint tool built for exactly this gap. It checks 20+ rules across four areas: coverage-methodology soundness, sampling and cross-coverage performance, style and maintainability, and constructs that are legal SystemVerilog but unsupported or ill-defined under Verilator specifically.

This talk walks through the rule set, how each pattern is detected in SystemVerilog source, and worked examples of what gets caught — a masked bug, a false sense of completeness, a performance cliff, or a Verilator compatibility gap.

Repo: https://github.com/AsFigo/FCOVLint

 PyUVM

Yogish Sekhar

Making pyuvm Usable for Industrial Verification

Abstract & Speaker Bio

pyuvm brings the UVM methodology to Python and cocotb, but a testbench cannot verify a real SoC without a working register abstraction layer. pyuvm's register package was structurally incomplete against IEEE 1800.2; while core access operations remained placeholders. Register models could be constructed but not meaningfully driven, which put any design with a non-trivial register map outside the reach of a Python-native flow.

Enhanced SV-UVM style reporting layer that provides severity, verbosity, report IDs, and centralised counts as an opt-in path over Python logging has also eased migration of existing methodology and supporting infrastructure without displacing Python-native practice. 

The obstacles to Python-native verification at industrial scale are no longer conceptual. They are specific, enumerable pieces of infrastructure, and they are being closed one merge at a time.

Bio: 

Yogish Sekhar is a semiconductor engineering executive who works across both sides of the discipline setting engineering direction and writing the code that delivers it. With over twenty years in the industry, he has worked on all aspects of verification for verifying silicon design to actully building the tools and the infrastructure that supports it. His current focus is the open-source verification stack. and he is the contributor of native FSM coverage to Verilator and is building the pyRAL framework. He serves on the DVCon Technical Programme Committee, holds an MBA from Chicago Booth, and writes on verification methodology, coverage as a risk instrument, and the changing economics of EDA.

SVALint

Manohar Natarajan, SiSethu

SystemVerilog Assertion linting to identify potential issues in SVA code and improve the quality and consistency of assertion-based verification.

Abstract & Speaker Bio

Founding mentor silicon Setu, Director,, ENADU CSP Foundation Senior Hardware and ASIC Verification Leader with 33 years of extensive experience driving end-to-end product development across the electronics hardware industry—from initial architecture concepts to successful silicon tape-outs. Core Expertise Domain Leadership: ASIC Front-End Design & Verification (20+ years), Microprocessors, Firmware, and Board-Level Design. Methodologies & Languages: Verilog, SystemVerilog, UVM, VMM, and RVM. Technology & Protocols: PCI/PCIe, Ethernet, LPDDR (2/3/4), Low-Power Design/Verification, and 802.11 WiFi. Architecture Experience: RISC-V, MIPS, and HP PA-RISC microprocessor cores. Track Record Successfully delivered over a dozen products from concept through production silicon. Deep specialization in complex, system-level integration, verification, and hardware-software co-design.

Venue

BHIVE Premium Bellandur Campus
Kadubisana Hall, Bellandur, Bengaluru, Karnataka 560103

Google Maps

Registration

The event is free to attend, but registration is required.

REGISTER NOW

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