Open-Source Chip Design & Verification Bootcamp — Programme & Speakers

Bengaluru | Monday, 31 August 2026 | 1:00–4:00 PM IST  | 8:30–11:30 AM BST (UK) | 9:30 AM–12:30 PM CEST (Central Europe)

REGISTER NOW - https://tinyurl.com/asfigoblr26  

Following our earlier announcement, the programme and speakers for the AsFigo Open-Source Chip Design & Verification Bootcamp are now taking shape.

For background and the story behind this event, see our earlier post.

Event Details

AsFigo invites working professionals, researchers, students and semiconductor enthusiasts to participate in this interactive technical meetup focused on open-source chip design and verification.

  • Date: Monday, 31 August 2026
  • Time: 1:00–4:00 PM IST | 8:30–11:30 AM BST (UK) | 9:30 AM–12:30 PM CEST (Central Europe)
  • Format: Hybrid
  • Host: AsFigo
  • In-person: BHIVE Premium Bellandur Campus, Ratan Tata Conf room | Ground Floor; Bellandur, Bengaluru
  • Online: Joining details will be shared with registered participants.

REGISTER NOW - https://tinyurl.com/asfigoblr26 

Programme

RustDV — The UVM in Rust

Rae Salemi

An exploration of bringing the UVM methodology to Rust and what Rust-based verification can offer to the open-source verification ecosystem.

Abstract & Speaker Bio

Ray Salemi is a 30-year veteran of the high-tech industry, with experience leading engineering, customer support and sales teams. He is an expert verification engineer, consultant, author and the creator of pyUVM, bringing UVM concepts to Python. Ray has authored several books on verification, including The UVM Primer, Python for RTL Verification, and Rust for RTL Verification. His work spans SystemVerilog/UVM, Python, cocotb, pyUVM and now Rust-based RTL verification. He is also a teacher and continues to contribute to verification education and the open-source verification community.

Kepler-Formal

Noam Cohen

An introduction to Kepler-Formal and its approach to open-source formal verification.

Abstract & Speaker Bio

kepler formal is an open source formal verification tool targeting industrial grade designs. For a long time, one of the crucial items missing in the open silicon ecosystem has been formal verification solutions capable of verifying modern scale architectures. kepler formal provides exactly that, with an advanced multi threaded C++ core that can handle even large designs in a timely fashion. In this talk, we will present the tool and its use model, as well as our roadmap in terms of format support and features.

Noam Cohen is the Co-Founder and CTO of keplertech.io. Throughout his corporate career, he led R&D teams at SNPS and Siemens, dedicated to compiler development for hardware prototyping and emulation, with a focus on optimizing solutions to NP-hard problems such as partitioning, placement, and routing, and with an emphasis on high performance computing. After 10 years with the EDA industry leaders, he co-founded keplertech.io with the aim of introducing innovation in both technology and user experience to hardware design software tools.

FCOVLint

VerifWorks

Functional-coverage linting aimed at identifying common coverage modelling issues before they become misleading or costly coverage results.

Abstract & Speaker Bio

Details to be added.

UVM + Verilator / UVMLint

AsFigo

Practical experience using UVM with Verilator, the challenges encountered, and how UVMLint can help identify portability and verification issues.

Abstract & Speaker Bio

Details to be added.

PyUVM

Yogish Sekhar

Recent updates to Python-UVM and Verilator

Abstract & Speaker Bio

Details to be added.

SVALint

SiSethu

SystemVerilog Assertion linting to identify potential issues in SVA code and improve the quality and consistency of assertion-based verification.

Abstract & Speaker Bio

Details to be added.

Venue

BHIVE Premium Bellandur Campus
Kadubisana Hall, Bellandur, Bengaluru, Karnataka 560103

Google Maps

Registration

The event is free to attend, but registration is required.

REGISTER NOW

Comments

Post a Comment

Popular posts from this blog

Cracking the UVM-Verilator Code: 50+ IPs, AI Guardrails, and the Open-Source North Star

UVM on Verilator Isn’t Impossible. It’s Just Hard. We Did It Anyway. The “standard” line in the industry: UVM and Verilator don’t mix. Enterprise-grade open-source verification is a fantasy. So we put that claim under load. ✔ 50+ production UVCs ported ✔ 35 + non-obvious failure modes uncovered ✔ Converted into UVMLint and SVALint rules ✔ AI guardrails to prevent regressions This post is the why and what; the how and numbers are for the room at Hacker Dojo.  This is production-grade code—the kind that tapes out chips—running on open-source infrastructure. The implication is bigger than a port: Reduced dependency on closed ecosystems. Negotiating leverage with EDA vendors. Strategic control over your verification stack. If you’re a semiconductor company exploring Verilator for serious IP, don’t start from scratch. Start from the team that already mapped the minefield. 📅 Join us at the Hacker Dojo Next Thursday, the AsFigo team...
Read more

Call for Collaboration: Seeking Public UVM Environments for Verilator 5.0+ Porting

The transition of SystemVerilog UVM environments to open-source simulators presents specific technical challenges. While Verilator 5.0+ has expanded support for various SystemVerilog constructs, the industry still lacks a documented and repeatable path for certain UVM-specific behaviors. In parallel, we aim to curate a public vault of UVM repositories that have been successfully ported to Verilator. AsFigo is initiating a collaborative effort to document these gaps, and we are looking for engineers, researchers, and students to contribute original UVM codebases to this effort.  Link to Google Form: Submit Your code base The Technical Focus This effort intentionally moves beyond minimal or illustrative examples. We are seeking unique, original UVM implementations that reflect realistic UVM environments and non-trivial SystemVerilog usage found in real-world verification flows. Infrastructure Components: Memo...
Read more

Breaking the License Barrier: The World’s First UVM + Verilator Hands-On Bootcamp - Mar-1, Sunday 3-5 PM PST

Remote link:  AsFigo UVM Verilator Bootcamp | Meeting-Join | Microsoft Teams For decades, the power of UVM (Universal Verification Methodology) has been locked behind the high-cost gates of commercial simulators. At AsFigo , we believe the future of silicon verification belongs to the community. We are breaking those gates down to empower a new generation of verification engineers. A Community Milestone The dream of open-source UVM is the result of a massive, multi-year industry effort. Foundations laid by the CHIPS Alliance, DARPA, Google, and Antmicro have reached a critical tipping point. This movement was fueled by the relentless technical contributions of pioneers such as Wilson Snyder, Geza Lore, Krzysztof Bieganski, et al. , whose work over the last several years made the "impossible" possible. The public breakthrough for UVM support in Verilator was announced in late 2023. On that very day, we at AsFigo successfully ported a complete APB UVC and...
Read more