AsFigo - enabling opensource chip design and verification.

At the Verification Futures 2026 conference at the University of Reading, a distinct shift was evident on the floor. While traditional vendor tracks dominated their usual slots, the parallel sessions focused on open-source and license-free verification tools drew a heavily engaged technical crowd. The conversations between engineers like Srinivasan Venkataramanan and core Verilator maintainer Geza Lore centered on a major milestone: the real-world production stability of running Universal Verification Methodology (UVM) natively on Verilator's public master branch. Nearby, discussions with contributors like Yogish Sekhar tracked how this foundation is now letting developers expand into native FSM code coverage extraction and advanced random constraint solving engines. But this current stability wasn't achieved through sweeping architectural changes. It came down to breaking a single, frustrating bottleneck earlier this year: the time-0 scheduling deadlock. The Ba...

The Invisible Include: Why SystemVerilog Migration Drag Demands a "Build Your Own Linter" (BYOL) Approach Tool migration is rarely a weekend project. When a team decides to switch SystemVerilog (SV) simulators—whether for faster execution, better coverage metrics, or licensing reasons—the expectation is usually a straightforward port. The RTL compiles in Tool A, so it should compile in Tool B, right? Then reality sets in. The migration timeline begins to stretch, not because of major architecture rewrites, but because of a grinding stream of minor environment and language compliance discrepancies. One of the most elusive "gotchas" in large codebases stems from how different simulators handle a seemingly simple task: finding an include file. The Local Include Trap Consider a standard file structure where an RTL file includes a local header located in the exact same directory: src/ └── core/ ├── cpu_top.sv └── cpu_defines.svh Inside cpu_top.sv ,...