Open-Source Chip Design & Verification bootcamp: Bengaluru, 31 August 2026

AsFigo is organising a 3-hour hybrid bootcamp on open-source chip design and verification in Bengaluru on Monday, 31 August 2026, immediately ahead of DVCon India 2026.

Date: Monday, 31 August 2026
Time: 1:00–4:00 PM IST
Location: Bengaluru, ORR / Bellandur area — venue to be confirmed
Format: Hybrid
Cost: Free to attend
Registration: Required

The event brings together a deliberately diverse set of open-source verification projects and approaches — from UVM and Verilator to Rust-based verification, formal, functional-coverage linting, OSVVM and SystemVerilog Assertions.

The aim is not to promote one particular tool or methodology. It is to bring together people working on different parts of the ecosystem and explore what is becoming possible with open-source verification.

A journey that started well before this event

AsFigo's work in open-source verification builds on a much longer history in design verification.

Our founders, Ajeetha Kumari and Srinivasan Venkataramanan, have been involved in verification in India since CVC was established in 2004, followed by VerifWorks in 2016.

Since AsFigo was established in the UK in late 2022, we have increasingly focused on open-source chip design and verification while continuing to work with the wider India and international verification communities.

A major part of that journey has been UVM + Verilator.

Back in 2023, we took a real UVC and attempted to port it to Verilator, documenting the practical issues encountered along the way. Porting a complete UVC to Verilator + UVM

That work grew considerably. By 2026, we had worked through 50+ production UVCs and identified 35+ non-obvious failure modes, turning many of those lessons into UVMLint and SVALint rules. Cracking the UVM-Verilator Code: 50+ IPs, AI Guardrails, and the Open-Source North Star

Some of the challenges also required working with the Verilator development community to isolate and fix issues in the simulator itself. The resulting progress towards stable UVM execution on mainline Verilator is an example of what can happen when users, developers and maintainers work together. Verification Futures 2026: The Engineers and Innovations Driving Open-Source EDA

Alongside this, our work on UVMLint and SVALint has grown from practical verification problems into open-source tooling for static analysis of verification code.

From DVCon US to DAC — and now Bengaluru

This Bengaluru event is part of a continuing series of open-source verification activities.

Around DVCon US 2026, AsFigo organised an open-source UVM + Verilator bootcamp, participated in the official Open-Source BOF, and subsequently held a Verilator + UVM event in Mountain View.

At DAC 2026, AsFigo participated in the Open-Source EDA BOF, including work around SVALint and open-source SVA linting. We also held a San Diego meetup focused on UVMLint, SVALint and related open-source verification work. AsFigo at DAC: AI Panel & Open-Source SVA Linting

Now we are bringing that conversation to Bengaluru.

AsFigo is also organising an Open-Source BOF at DVCon India 2026, continuing the discussion within the main conference. This separate event provides an opportunity to go broader and bring together projects and communities that don't necessarily fit into a conventional conference session.

What we'll cover

The current programme includes approximately 30-minute sessions on:

  • RustDV — The UVM in Rust

  • Kepler-Formal — Noam Cohen

  • FCOVLint

  • OSVVM

  • UVM + Verilator / UVMLint — AsFigo

  • SVALint

Speakers for the remaining sessions are being finalised.

The diversity is intentional. Open-source verification is no longer about a single simulator or methodology. Different projects are approaching simulation, formal verification, coverage, verification languages and static analysis from different directions.

We want to bring some of those efforts into the same conversation.

Who should attend?

The event is open to anyone interested in open-source chip design and verification, including:

  • verification engineers and architects

  • open-source EDA developers and contributors

  • students and researchers

  • academics

  • semiconductor startups

  • engineers exploring alternatives to proprietary verification infrastructure

  • experienced engineers looking to share or apply their knowledge

You can attend in person in Bengaluru or online from anywhere.

We are not aiming for a large conference. We would rather have a focused group of people who are genuinely interested in building, using and contributing to open-source verification.

Registration details will follow shortly.

More details and registration: [link to be added]

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