Verification Futures 2026: The Engineers and Innovations Driving Open-Source EDA

At the Verification Futures 2026 conference at the University of Reading, a distinct shift was evident on the floor. While traditional vendor tracks dominated their usual slots, the parallel sessions focused on open-source and license-free verification tools drew a heavily engaged technical crowd.

The conversations between engineers like Srinivasan Venkataramanan and core Verilator maintainer Geza Lore centered on a major milestone: the real-world production stability of running Universal Verification Methodology (UVM) natively on Verilator's public master branch. Nearby, discussions with contributors like Yogish Sekhar tracked how this foundation is now letting developers expand into native FSM code coverage extraction and advanced random constraint solving engines.

But this current stability wasn't achieved through sweeping architectural changes. It came down to breaking a single, frustrating bottleneck earlier this year: the time-0 scheduling deadlock.

The Backstory: The Time-0 Wall

In early 2026, an ambitious engineering push was underway to port 50 commercial-grade Universal Verification Components (UVCs)—built on standard UVM 1.1d / IEEE 1800.2 constructs—directly onto the public mainline of Verilator.

The code compiled, but simulation execution ground to an immediate halt. Due to complex SystemVerilog scheduling dependencies and dynamic class initialization overhead, the majority of simulations exited or hung immediately at time-0 via #0 delay race conditions.

Human Domain Expertise vs. The Machine

This bottleneck provided a stark reality check for modern debugging workflows. Pushing Verilator’s massive, highly interconnected C++ source tree through advanced LLMs (like Claude or Gemini) to find the root cause of the time-0 loop yielded nothing. The compiler’s internal dependency graphs are simply too complex for automated pattern-matching.

The resolution required traditional open-source friction: logging reproducible test cases on GitHub and initiating public technical discussions on LinkedIn to isolate the behavior. Recognizing the ecosystem block, Wilson Snyder coordinated with Geza Lore to dive into the backend scheduling mechanics.

The investigation ultimately identified a scheduler ordering issue that could be addressed with a relatively small patch:

  • The Reduced Testcase: Srini isolated the failure into a minimized testcase and logged a specific issue on the Verilator repository, turning a known abstract issue into an actionable bug.
  • Isolate the Race Condition: Geza used the testcase to trace the execution path and locate exactly where Verilator's event-ordering system was deadlocking dynamic class structures at initialization.
  • The 10-Line Patch: A precise 10-to-20 line fix was committed to the public master branch. The complexity wasn't the size of the patch, but knowing exactly which lines to alter.
  • The Mass Porting Sprint: With the scheduling gate unlocked, an extended engineering team in India crunched through the codebases, successfully porting 50 production-grade UVCs natively.
  • Proving the Scalability: The complete stack was stress-tested globally during Birds of a Feather (BoF) sessions and live, hands-on UVM bootcamps running over cloud infrastructure at DVCon US in February 2026.

This engineering journey explains why the atmosphere at Reading was so collaborative. The community moved from questioning if mainline Verilator could handle commercial UVM arrays, classes, and scheduling, to actively debating how to expand its feature set.

The UK Open-Source Verification Collective

While the Verilator time-0 patch was a major technical milestone, it didn’t happen in isolation. It is part of a rapidly expanding, highly collaborative movement within the UK semiconductor landscape. In fact, many of the well-known pioneers, core maintainers, and industrial anchors driving this open-source EDA shift were present at the University of Reading event, actively sharing insights across the technical tracks and networking sessions. This collective represents the backbone of that industrial transformation:

The Foundation & Pioneers

  • Simon Davidmann: Co-founder of Co-Design Automation; created Superlog—the foundational language donated and standardized to become modern SystemVerilog.
  • Simon Southwell: Virtual prototyping expert; pioneered early open-source host-to-RTL co-simulation models (vproc) that laid the groundwork for modern C++/RTL bridging.
  • lowRISC & Riverlane: Cambridge-based anchors whose rigorous silicon codebases (OpenTitan and quantum control systems) serve as the ultimate real-world "torture tests" for open EDA tools.

Core Engine & Compiler Infrastructure

  • Geza Lore: Core Verilator maintainer; responsible for the critical scheduling updates that resolved the time-0 deadlocks, and performance improvements.
  • Wilson Snyder: Lead maintainer of Verilator; managing the mainline infrastructure and coordinating core development priorities. Though Wilson was not at the event, we felt compelled to credit him!

Methodology, Tooling & Verification IP

  • Srinivasan Venkataramanan (AsFigo): Driving mainline VIP porting, maintaining ivl_uvm, integrating OVL with Icarus Verilog, managing SVUnit on Verilator, and upstreaming compiler patches for SystemVerilog array constraints.
  • Yogish Sekhar: Contributing native tool fixes to improve random constraint solving engines and expanding support for FSM (Finite State Machine) code coverage extraction.
  • Ajeetha Kumari (AsFigo): Developing deterministic static analysis rule sets for UVMLint and SVALint to flag unsupported SystemVerilog constructs pre-compilation.
  • Andrew Bond (Axelera AI): Developing and maintaining the Python-driven AVL (Apheleia Verification Library) ecosystem sitting on top of cocotb and Verilator.

Cloud Execution & Infrastructure

  • Isaar Ahmad (University of Bristol): Configuring the cloud-native AWS execution layers, FPGA setups, and RISC-V design targets that allowed large-scale workloads—like the recent DVCon 2026 bootcamps—to scale smoothly.

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