AsFigo - enabling opensource chip design and verification.

While our previous posts focused on the strategic "Why," this post addresses the "How." Porting 50+ production-grade UVCs wasn't a matter of simple recompilation. It was an exercise in uncovering the delta between commercial simulator "permissiveness" and the strict reality of the SystemVerilog LRM and the Verilator execution model. Here are the some of the primary technical roadblocks we mapped and cleared.  You can learn lot more at our upcoming event on Thursda y, get your tickets today:  https://buytickets.at/asfigo/2091884   1. Strict LRM & Parsing Enforcement Commercial tools have historically been "lazy" with LRM enforcement. Verilator is not. Code that has run for years in proprietary silos often fails immediately here due to: SVA: Basic temporals do work, not complex ones. We have ported AHB, APB and AXI4-Lite SVA IPs to Verilator, so though this sounds very limiting, in reality, it is not that bad! Range Syntax: Not so...

UVM on Verilator Isn’t Impossible. It’s Just Hard. We Did It Anyway. The “standard” line in the industry: UVM and Verilator don’t mix. Enterprise-grade open-source verification is a fantasy. So we put that claim under load. ✔ 50+ production UVCs ported ✔ 35 + non-obvious failure modes uncovered ✔ Converted into UVMLint and SVALint rules ✔ AI guardrails to prevent regressions This post is the why and what; the how and numbers are for the room at Hacker Dojo.  This is production-grade code—the kind that tapes out chips—running on open-source infrastructure. The implication is bigger than a port: Reduced dependency on closed ecosystems. Negotiating leverage with EDA vendors. Strategic control over your verification stack. If you’re a semiconductor company exploring Verilator for serious IP, don’t start from scratch. Start from the team that already mapped the minefield. 📅 Join us at the Hacker Dojo Next Thursday, the AsFigo team...

In our previous post , we discussed the gap between AI "demos" and production-grade silicon. Today, we address the primary friction point preventing the industry from scaling AI-driven verification: The License Tax.  Registration:   https://forms.gle/WX6Hqwew2HfwDFmF8  The Math of Iteration "Agentic AI"—where autonomous loops generate, test, and fix RTL—relies on high-frequency iteration. For an AI agent to "learn" a fix or optimize a module, it may need to run hundreds or thousands of cycles through a verification engine. In a traditional environment, this is an economic impossibility. If every iterative trial pings a commercial tool seat—often costing upwards of $100,000 per license —the cost of the "agentic workforce" scales faster than its productivity. To make AI ROI viable, we must decouple the high-volume iterative cleaning from the high-cost final sign-off. The Production Milestone: Verilator + UVM is becoming a ...

🚀 The AsFigo GitHub Challenge: Earn Your Seat We are looking for committed builders to join us at JCNC on March 1st for the world’s first UVM Verilator Bootcamp. We want to see your UVM fundamentals in action, and in return, we’re offering a path to join us through technical contribution. The Reward We are opening 5 Complementary Seats ($40 value each) for top contributors who demonstrate their work in the open-source ecosystem. The Challenge: Prove Your Build To be eligible for a complementary seat, you must showcase your UVM skills on GitHub: The Content: A public GitHub repository featuring 2 unique, small UVCs (or a mini-environment) you have built. The Proof: Your repo must include a clean file list ( .f ) and a simulation log proving a "Pass" status from any simulator (e.g., EDA Playground). The Deadline: Submit your GitHub link by Sunday, Feb 22nd, 11:59 PM PST . Why Enter? ...

The "AI in EDA" conversation is currently dominated by two extremes: the hype of autonomous agents and the reality of legacy verification constraints. While AI can generate code in seconds, the friction begins the moment that code hits a verification environment. Whether it’s the cost of commercial licenses or the risk of unvetted UVM sequences, the gap between a "cool demo" and a Production-Ready flow is wider than most realize. At DVCon 2026 , AsFigo is bridging that gap. We are hosting a Birds of a Feather (BoF) session to look at the full stack of Silicon-Ready AI . We’ve assembled a panel of industry veterans and disruptors to examine how we actually scale: The Workforce Shift: How global Centers of Excellence are integrating AI into existing UVM teams. The Agentic Loop: Startup founders on building autonomous verification cycles that actually close coverage. The Infrastructure: Solving the bottleneck of simulation licenses and specialized...

Remote link:  AsFigo UVM Verilator Bootcamp | Meeting-Join | Microsoft Teams For decades, the power of UVM (Universal Verification Methodology) has been locked behind the high-cost gates of commercial simulators. At AsFigo , we believe the future of silicon verification belongs to the community. We are breaking those gates down to empower a new generation of verification engineers. A Community Milestone The dream of open-source UVM is the result of a massive, multi-year industry effort. Foundations laid by the CHIPS Alliance, DARPA, Google, and Antmicro have reached a critical tipping point. This movement was fueled by the relentless technical contributions of pioneers such as Wilson Snyder, Geza Lore, Krzysztof Bieganski, et al. , whose work over the last several years made the "impossible" possible. The public breakthrough for UVM support in Verilator was announced in late 2023. On that very day, we at AsFigo successfully ported a complete APB UVC and...

The transition of SystemVerilog UVM environments to open-source simulators presents specific technical challenges. While Verilator 5.0+ has expanded support for various SystemVerilog constructs, the industry still lacks a documented and repeatable path for certain UVM-specific behaviors. In parallel, we aim to curate a public vault of UVM repositories that have been successfully ported to Verilator. AsFigo is initiating a collaborative effort to document these gaps, and we are looking for engineers, researchers, and students to contribute original UVM codebases to this effort.  Link to Google Form: Submit Your code base The Technical Focus This effort intentionally moves beyond minimal or illustrative examples. We are seeking unique, original UVM implementations that reflect realistic UVM environments and non-trivial SystemVerilog usage found in real-world verification flows. Infrastructure Components: Memo...