AsFigo - enabling opensource chip design and verification.

This first installment of our DVCon US ’26 video series dives straight into a reality check that often gets lost in the hype of generative AI: The cost of a single "thought." In this segment, Srini (AsFigo) sits down with Asif ETV (HPCINFRA) to discuss why the transition to AI-native chip design isn't just a software challenge—it’s a massive infrastructure and economic hurdle. Watch the Full Segment :  In this 3-minute clip, watch Asif and Srini break down the economic reality of the modern AI-EDA stack and why optimizing for the right infrastructure is the only way to stay within budget while bringing AI into production. The Cost Explosion: Doing the Math on Hallucinations When we talk about "Agentic AI" in EDA, we imagine autonomous loops of design and verification. But as Asif ETV points out, the meter is always running, and it’s running faster than many teams realize. Sharing a startling metric from recent infrastructure experiments, the m...

If you missed the Birds of a Feather (BoF) session at DVCon US '26 in Santa Clara, hosted by AsFigo , you missed a critical conversation about the structural barrier facing silicon design: AI is currently too expensive to fail. While Large Language Models (LLMs) have become proficient at generating Verilog syntax, the industry is hitting a wall we call the $100k AI-EDA Bottleneck . To move from "cool demos" to production-ready chip design collaterals (RTL, SVA, UVM, SDC, Synthesis, Physical design scripts all the way upto GDS-II), we must solve the hallucination problem without bankrupting the project on EDA licenses. The Problem: The "EDA License Tax" on Reasoning Agentic AI—systems that autonomously iterate on design and verification—thrives on a "Trial-Error-Correct" loop. An agent might require thousands of simulation or linting runs to prune logic hallucinations and refine a complex IP block. In a traditional workflow, every on...