AsFigo - enabling opensource chip design and verification.

Bengaluru | Monday, 31 August 2026 | 1:00–4:00 PM IST  | 8:30–11:30 AM BST (UK) | 9:30 AM–12:30 PM CEST (Central Europe) REGISTER NOW - https://tinyurl.com/asfigoblr26    Following our earlier announcement, the programme and speakers for the AsFigo Open-Source Chip Design & Verification Bootcamp are now taking shape. For background and the story behind this event, see our earlier post . Event Details AsFigo invites working professionals, researchers, students and semiconductor enthusiasts to participate in this interactive technical meetup focused on open-source chip design and verification. Date: Monday, 31 August 2026 Time: 1:00–4:00 PM IST | 8:30–11:30 AM BST (UK) | 9:30 AM–12:30 PM CEST (Central Europe) Format: Hybrid Host: AsFigo In-person: BHIVE Premium Bellandur Campus, Ratan Tata Conf room | Ground Floor; Bellandur, Bengaluru Online: Joining details will be shared with registered participants. REGISTER NOW -...

AsFigo is organising a 3-hour hybrid bootcamp on open-source chip design and verification in Bengaluru on Monday, 31 August 2026, immediately ahead of DVCon India 2026. Date: Monday, 31 August 2026 Time: 1:00–4:00 PM IST Location: Bengaluru, ORR / Bellandur area — venue to be confirmed Format: Hybrid Cost: Free to attend Registration: Required The event brings together a deliberately diverse set of open-source verification projects and approaches — from UVM and Verilator to Rust-based verification, formal, functional-coverage linting, OSVVM and SystemVerilog Assertions. The aim is not to promote one particular tool or methodology. It is to bring together people working on different parts of the ecosystem and explore what is becoming possible with open-source verification. A journey that started well before this event AsFigo's work in open-source verification builds on a much longer history in design verification. Our founders, Ajeetha Kumari and Srinivasan Venkataramanan, ha...

Why Regex Is the Wrong Abstraction for SystemVerilog Coverage Linting When building a lint rule for SystemVerilog functional coverage, it is tempting to start with a regular expression. The problem can initially appear simple: find array-based coverpoint bins, calculate how many bins they expand into, and report a violation if the count exceeds the supported limit. A first implementation might read the source file, remove comments, and search for patterns such as bins foo[] = {[0:2048]}; . As a first-cut implementation, this is perfectly reasonable. It is small, easy to prototype, and useful for validating the basic rule logic. The problem is that regular expressions operate on source text , while a lint rule needs to reason about language structure . Consider: bins values[] = { [0:2048], [3000:4000] }; The rule now needs to understand that this is one array-bin declaration containing multiple ranges, and calculate the expansion represented by those ranges. A re...